UPaRC ultra-fast power-aware reconfiguration controller

• Published in: Proceedings of the Conference on Design, Automation and Test in Europe pp. 1373 - 1378
• Main Authors: Bonamy, Robin, Pham, Hung-Manh, Pillement, Sébastien, Chillet, Daniel
• Format: Conference Proceeding
• Language: English
• Published: San Jose, CA, USA EDA Consortium 12.03.2012
• Series: ACM Conferences
• Subjects: Hardware > Electronic design automation > Physical design (EDA); Hardware > Hardware validation; Hardware > Very large scale integration design > Application-specific VLSI designs; dynamic partial reconfiguration; ICAP; rapid reconfiguration speed; power consumption
• ISBN: 3981080181; 9783981080186
• DOI: 10.5555/2492708.2493044

Dynamically reconfigurable architectures, which can offer high performance, are increasingly used in different domains. High-speed reconfiguration process can be carried out by operating at high frequency but can also augment the power consumption. Thus the effort on increasing performance by accelerating the reconfiguration should take into account power consumption constraints. In this paper, we present an ultra-fast power-aware reconfiguration controller (UPaRC) to boost the reconfiguration throughput up to 1.433 GB/s. UPaRC can not only enhance the system performance, but also auto-adapt to various performance and consumption conditions. This could enlarge the range of applications and optimize for each selected application during run-time. An investigation of reconfiguration bandwidths at different frequencies and with different bitstream sizes are experimentally quantified and presented. The power consumption measurements are also realized to emphasize energy-efficiency of UPaRC over state-of-the-art reconfiguration controllers---up to 45 times more efficient.