SystemC as completing pillar in industrial OVM based verification environments

This paper presents a novel TLM verification approach utilizing TLM+ as a reference model and providing a systematic path to RTL simulation as well. The approach is based on SystemC only but follows the established structure on an OVM testbench. Industrial relevant aspects as use of standards, early...

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Bibliographic Details
Published inProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis pp. 307 - 312
Main Authors Ecker, Wolfgang, Esen, Volkan, Velten, Michael, Timisescu, Tudor
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 07.10.2012
SeriesACM Conferences
Subjects
Applied computing > Physical sciences and engineering > Engineering
systemc
testbench
verification
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Summary:This paper presents a novel TLM verification approach utilizing TLM+ as a reference model and providing a systematic path to RTL simulation as well. The approach is based on SystemC only but follows the established structure on an OVM testbench. Industrial relevant aspects as use of standards, early verification, and re-use of design items are established in this way.
ISBN:1450314260
9781450314268
DOI:10.1145/2380445.2380496