S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity

Symmetry and matching between critical building blocks have a significant impact on analog system performance. However, there is limited research on generating system level symmetry constraints. In this paper, we propose a novel method of detecting system symmetry constraints for analog circuits wit...

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Bibliographic Details
Published in2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) pp. 193 - 198
Main Authors Liu, Mingjie, Li, Wuxi, Zhu, Keren, Xu, Biying, Lin, Yibo, Shen, Linxiao, Tang, Xiyuan, Sun, Nan, Pan, David Z.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2020
Subjects
Analog circuits
Asia
Circuit topology
Circuits and systems
Design automation
System performance
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Summary:Symmetry and matching between critical building blocks have a significant impact on analog system performance. However, there is limited research on generating system level symmetry constraints. In this paper, we propose a novel method of detecting system symmetry constraints for analog circuits with graph similarity. Leveraging spectral graph analysis and graph centrality, the proposed algorithm can be applied to circuits and systems of large scale and different architectures. To the best of our knowledge, this is the first work in detecting system level symmetry constraints for analog and mixed-signal (AMS) circuits. Experimental results show that the proposed method can achieve high accuracy of 88.3% with low false alarm rate of less than 1.1% in largescale AMS designs.
ISSN:2153-697X
DOI:10.1109/ASP-DAC47756.2020.9045109