Vapor–Liquid–Solid Growth of Morphology-Tailorable WS2 toward P‑Type Monolayer Field-Effect Transistors
Although substantial efforts have been made, controllable synthesis of p-type WS2 remains a challenge. In this work, we employ NaCl as a seeding promoter to realize vapor–liquid–solid (VLS) growth of p-type WS2. Morphological evolution, including a one-dimensional (1D) nanowire to two-dimensional (2...
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Published in | ACS applied materials & interfaces Vol. 14; no. 40; pp. 45716 - 45724 |
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Main Authors | , , , , , |
Format | Journal Article |
Language | English |
Published |
American Chemical Society
12.10.2022
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Subjects | |
Online Access | Get full text |
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Summary: | Although substantial efforts have been made, controllable synthesis of p-type WS2 remains a challenge. In this work, we employ NaCl as a seeding promoter to realize vapor–liquid–solid (VLS) growth of p-type WS2. Morphological evolution, including a one-dimensional (1D) nanowire to two-dimensional (2D) planar domain and 2D shape transition of WS2 domains, can be well-controlled by the growth temperature and sulfur introduction time. A high growth temperature is required to enable planar growth of 2D WS2, and a sulfur-rich environment is found to facilitate the growth of high-quality WS2. Raman and photoluminescence (PL) mappings demonstrate uniform crystallinity and high quantum efficiency of VLS-grown WS2. Moreover, monolayer WS2-based field-effect transistors (FETs) are fabricated, showing p-type conducting behavior, which is different from previous reported n-type FETs from WS2 grown by other methods. First-principles calculations show that the p-type behavior originates from the substitution of Na at the W site, which will form an additional acceptor level above the valence band maximum (VBM). This facile VLS growth method opens the avenue to realize the p–n WS2 homojunctions and p/n-WS2-based heterojunctions for monolayer wearable electronic, photonic, optoelectronic, and biosensing devices and should also be a great benefit to the development of 2D complementary metal–oxide–semiconductor (CMOS) circuit applications. |
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Bibliography: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
ISSN: | 1944-8244 1944-8252 |
DOI: | 10.1021/acsami.2c13812 |