Automated design of self-adjusting pipelines

We propose a self-adjusting pipeline structure to enhance chip performance and robustness considering the effects of process variations. We achieve this by introducing delay sensors to monitor internal timing violations within a pipeline stage and variable clock skew buffers to adjust the timing of...

Full description

Saved in:
Bibliographic Details
Published in2008 45th ACM/IEEE Design Automation Conference pp. 211 - 216
Main Authors Long, Jieyi, Memik, Seda Ogrenci
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 08.06.2008
IEEE
SeriesACM Conferences
Subjects
Circuit simulation
Clocks
Computer systems organization > Dependable and fault-tolerant systems and networks
Computerized monitoring
Delay
Delay Monitoring
General and reference > Cross-computing tools and techniques > Performance
Hardware
Manufacturing
Networks > Network performance evaluation
Pipelines
Robustness
Self-Adjusting
Stochastic processes
Timing
Variable Clock Skews
variable clock skews
delay monitoring
self-adjusting
Online AccessGet full text

Cover

More Information
Summary:We propose a self-adjusting pipeline structure to enhance chip performance and robustness considering the effects of process variations. We achieve this by introducing delay sensors to monitor internal timing violations within a pipeline stage and variable clock skew buffers to adjust the timing of the pipeline stage based on the feedback from the delay sensors. Furthermore, we formulate the delay sensor insertion and variable clock skew configuration problem as a stochastic mixed-integer programming problem and propose a simulated-annealing based algorithm to solve it. A comparison between the designs with and without the self-adjusting enhancement reveals that, we are able to improve the average performance of a batch of chips by 9.5%.
ISBN:1605581151
9781605581156
ISSN:0738-100X
DOI:10.1145/1391469.1391523