Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching

• Published in: 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) pp. 251 - 264
• Main Authors: Wu, Lingxi, Sharifi, Rasool, Lenjani, Marzieh, Skadron, Kevin, Venkat, Ashish
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.06.2021
• Subjects: Accelerator; Bioinformatics; Computer architecture; Genomics; Graphics processing units; Hardware; Pipelines; Processing-in-memory; Random access memory; Throughput
• ISSN: 2575-713X
• DOI: 10.1109/ISCA52012.2021.00028

The rapid influx of biosequence data, coupled with the stagnation of the processing power of modern computing systems, highlights the critical need for exploring high-performance accelerators that can meet the ever-increasing throughput demands of modern bioinformatics applications. This work argues that processing in memory (PIM) is an effective solution to enhance the performance of k-mer matching, a critical bottleneck stage in standard bioinformatics pipelines, that is characterized by random access patterns and low computational intensity.This work proposes three DRAM-based in-situ k-mer matching accelerator designs (one optimized for area, one optimized for throughput, and one that strikes a balance between hardware cost and performance), dubbed Sieve, that leverage a novel data mapping scheme to allow for simultaneous comparisons of millions of DNA base pairs, lightweight matching circuitry for fast pattern matching, and an early termination mechanism that prunes unnecessary DRAM row activation to reduce latency and save energy. Evaluation of Sieve using state-of-the-art workloads with real-world datasets shows that the most aggressive design provides an average of 326x/32x speedup and 74X/48x energy savings over multi-core-CPU/GPU baselines for k-mer matching.