A parallelized way to provide data encryption and integrity checking on a processor-memory bus

• Published in: 2006 43rd ACM/IEEE Design Automation Conference pp. 506 - 509
• Main Authors: Elbaz, Reouven, Torres, Lionel, Sassatelli, Gilles, Guillemin, Pierre, Bardouillet, Michel, Martinez, Albert
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 24.07.2006; IEEE
• Series: ACM Conferences
• Subjects: Algorithm design and analysis; Algorithms; Applied computing > Computers in other domains > Personal computers and PC applications; Architectures; Bus Encryption; Computational modeling; Cryptography; Data Confidentiality and Integrity; Data security; Design; Engines; Information security; Information systems > Data management systems > Data structures > Data layout > Data encryption; Microcomputers; Portable computers; Security; Security and privacy > Cryptography; Splicing; System-on-a-chip; Theory of computation > Computational complexity and cryptography; Verification; architectures; bus encryption; data confidentiality and integrity
• ISBN: 1595933816; 9781595933812
• ISSN: 0738-100X
• DOI: 10.1145/1146909.1147042

This paper describes a novel engine, called PE-ICE (Parallelized Encryption and Integrity Checking Engine), enabling to guarantee confidentiality and integrity of data exchanged between a SoC (System on Chip) and its external memory. The PE-ICE approach is based on an existing block-encryption algorithm to which the integrity checking capability is added. Simulation results show that the performance overhead of PE-ICE remains low (below 4%) compared to block-encryption-only systems (which provide data confidentiality only).