Automatic synthesis of compressor trees reevaluating large counters

• Published in: Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 16-20 Apr. 2007 pp. 443 - 448
• Main Authors: Verma, Ajay K., Ienne, Paolo
• Format: Conference Proceeding
• Language: English
• Published: San Jose, CA, USA EDA Consortium 16.04.2007
• Series: ACM Conferences
• ISBN: 3981080122; 9783981080124
• DOI: 10.5555/1266366.1266461

Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic synthesisers, which play a fundamental role in design today, play a minor role on most arithmetic circuits, performing some local optimisations but hardly improving the overall structure of arithmetic components. Architectural optimisations have been often studied manually, and only in the case of very common building blocks such as fast adders and multi-input adders, ad-hoc techniques have been developed. A notable case is multi-input addition, which is the core of many circuits such as multipliers, etc. The most common technique to implement multi-input addition is using compressor trees, which are often composed of carry-save adders (based on (3 : 2) counters, i.e., full adders). A large body of literature exists to implement compressor trees using large counters. However, all the large counters were built by using full and half adders recursively. In this paper we give some definite answers to issues related to the use of large counters. We present a general technique to implement large counters whose performance is much better than the ones composed of full and half adders. Also we show that it is not always useful to use larger optimised counters and sometimes a combination of various size counters gives the best performance. Our results show 15% improvement in the critical path delay. In some cases even hardware area is reduced by using our counters.