Realtime wavelet video coder based on reduced memory accessing
In this paper, the VLSI implementation of a real-time EZW video coder is presented. The proposed architecture adopts a modified 2-D DWT subband decomposition scheme, with the purpose of reducing the transposition memory requirements of 2-D DWT. In addition, through the use of a parallelized partial...
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Published in | Proceedings of the 2001 Asia and South Pacific Design Automation Conference pp. 15 - 16 |
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Main Authors | , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
New York, NY, USA
ACM
30.01.2001
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Series | ACM Conferences |
Subjects | |
Online Access | Get full text |
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Summary: | In this paper, the VLSI implementation of a real-time EZW video coder is presented. The proposed architecture adopts a modified 2-D DWT subband decomposition scheme, with the purpose of reducing the transposition memory requirements of 2-D DWT. In addition, through the use of a parallelized partial zerotree EZW scheme, temporary buffer requirements between the DWT and EZW modules are also reduced. The video encoder is integrated in a 0.35 um 3LM chip by using 341 K transistors on a 4.93 x 4.93 mm2 die. |
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Bibliography: | SourceType-Conference Papers & Proceedings-1 ObjectType-Conference Paper-1 content type line 25 |
ISBN: | 0780366344 9780780366343 |
DOI: | 10.1145/370155.370211 |