Challenges in gate level modeling for delay and SI at 65nm and below

In this paper we review the prior art and recent advances in the area of standard cell modeling for delay and noise analyses, suggest a taxonomy of different cell models, and discuss their strengths and weaknesses. We also discuss challenges in cell modeling for delay and noise analyses arising in n...

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Bibliographic Details
Published in2008 45th ACM/IEEE Design Automation Conference pp. 468 - 473
Main Authors Keller, Igor, Tam, King Ho, Kariat, Vinod
Format Conference Proceeding
LanguageEnglish
Published New York, NY, USA ACM 08.06.2008
IEEE
SeriesACM Conferences
Subjects
Applied computing > Physical sciences and engineering > Engineering
Circuit simulation
CMOS technology
Crosstalk
Delay
Delay Calculation
Gate Characterization
Gate Modeling
Integrated circuit modeling
Permission
Semiconductor device measurement
Semiconductor device modeling
Silicon
Timing
gate modeling
delay calculation
gate characterization
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Summary:In this paper we review the prior art and recent advances in the area of standard cell modeling for delay and noise analyses, suggest a taxonomy of different cell models, and discuss their strengths and weaknesses. We also discuss challenges in cell modeling for delay and noise analyses arising in new submicron process nodes.
ISBN:1605581151
9781605581156
ISSN:0738-100X
DOI:10.1145/1391469.1391590