Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology

• Published in: Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08) pp. 15 - 20
• Main Authors: Suzuki, Hiroaki, Kurimoto, Masanori, Yamanaka, Tadao, Takata, Hidehiro, Makino, Hiroshi, Shinohara, Hirofumi
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 11.08.2008; IEEE
• Series: ACM Conferences
• Subjects: body-biasing; Circuit testing; CMOS technology; device variability suppression; Fuses; Hardware > Emerging technologies; Hardware > Very large scale integration design; Leakage current; leakage current reduction; Master-slave; MOS devices; post-silicon programming; Programmable control; Read only memory; Switches; Variable structure systems; body-biasing; post-silicon programming; device variability suppression; leakage current reduction
• ISBN: 9781605581095; 1605581097; 9781424486342; 1424486343
• DOI: 10.1145/1393921.1393931

The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%.