Prototyping dynamic task migration on heterogeneous reconfigurable systems

• Published in: 2017 International Symposium on Rapid System Prototyping (RSP) pp. 16 - 22
• Main Authors: Wicaksana, Arief, Bourge, Alban, Muller, Olivier, Sasongko, Arif, Rousseau, Frédéric
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 19.10.2017
• Series: ACM Conferences
• Subjects: Computer systems organization > Architectures > Other architectures > Heterogeneous (hybrid) systems; Computer systems organization > Embedded and cyber-physical systems > System on a chip; Context; Dynamic scheduling; Field programmable gate arrays; Hardware; Hardware > Integrated circuits > Reconfigurable logic and FPGAs > Hardware accelerators; Hardware > Integrated circuits > Reconfigurable logic and FPGAs > Reconfigurable logic applications; Heterogeneous FPGAs; Registers; Task analysis; Task Migration; Task-Specific Extraction; task-specific extraction; heterogeneous FPGAs; task migration
• ISBN: 9781450354189; 1450354181
• ISSN: 2150-5519
• DOI: 10.1145/3130265.3130316

Reconfigurable devices, such as FPGAs, have been known to offer an excellent performance and a high efficiency in computation. Due to their improving capacity and more efficient architecture recently, there are growing interests in using FPGAs as coprocessors in reconfigurable systems. However, FPGAs still lack the support in dynamic scheduling, e.g. to manage multiple tasks or users in a system. Performing runtime task relocation or load distribution is not possible unless the reconfigurable system supports dynamic task migration. Such ability requires the automation of configuration and context management in reconfigurable architecture, which is not available in the existing solutions. In this paper, we propose a framework for prototyping dynamic task migration between heterogeneous FPGAs. A task running on one FPGA can be suspended and resumed on another FPGA with different architecture. The extraction and restoration of FPGA registers and memory values are possible due to the task-specific extraction mechanism provided by the tasks. The proposed framework exploits a high-performance embedded processor tightly-coupled to an FPGA to automatically manage the configuration and context. It utilizes two popular heterogeneous reconfigurable systems in the implementation, Xilinx Zynq ZC706 and Altera Arria V SoC. Tests are performed using graphical and non-graphical benchmark applications and performance results are presented.