Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs

• Published in: 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers pp. 666 - 673
• Main Authors: Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2009
• Subjects: Circuit optimization; Circuit synthesis; Convergence; Design engineering; Energy consumption; Performance analysis; Permission; Process design; System-on-a-chip; Voltage
• ISSN: 1092-3152; 1558-2434
• DOI: 10.1145/1687399.1687523

Excessive supply voltage drops in a circuit may lead to significant circuit performance degradation and even malfunction. To handle this problem, existing power delivery aware placement algorithms model voltage drops as an optimization objective. We observe that directly minimizing voltage drops in an objective function might not resolve voltage-drop violations and might even cause problems in power-integrity convergence. To remedy this deficiency, in this paper, we propose new techniques to incorporate device power spreading forces into a mixed-size analytical placement framework. Unlike the state-of-the-art previous work that handles the worst voltage-drop spots one by one, our approach simultaneously and globally spreads all the blocks with voltage-drop violations to desired locations directly to minimize the violations. To apply the power force, we model macro current density and power rails for our placement framework to derive desired macro/cell locations. To further improve the solution quality, we propose an efficient mathematical transformation to adjust the power force direction and magnitude. Experimental results show that our approach can substantially improve the voltage drops, wirelength, and runtime over the previous work.