Logic Computing Field-Effect Transistors Based on a Monolayer WSe2 Homojunction for the Semi-adder and Decoder

• Published in: Nano letters Vol. 24; no. 35; pp. 11132 - 11139
• Main Authors: Li, Xueping, Wang, Zhuojun, Tang, Xiaojie, Yuan, Peize, Li, Lin, Shen, Chenhai, Jiang, Yurong, Song, Xiaohui, Xia, Congxin
• Format: Journal Article
• Language: English
• Published: American Chemical Society 04.09.2024
• Subjects: split gate; reconfigurable; logic gates
• ISSN: 1530-6984; 1530-6992; 1530-6992
• DOI: 10.1021/acs.nanolett.4c03556

Two-dimensional reconfigurable field-effect transistors (FETs) are promising candidates for next-generation computing hardware. However, exploring the cascade design of FETs for logic computing remains challenging. Here, by using density functional theory combined with the nonequilibrium Green’s function method, we design a 5 nm split-gate FET based on a monolayer WSe2 homojunction, which can implement dynamic polarity control in different gate configurations. The series array of two FETs shows a functional family of logic gates (NOR, AND, XOR, A̅B, and AB̅), and the semi-adder designed by the logic functions AND and XOR reduces the number of transistors by 66.7%. The parallel array of two FETs demonstrates reconfigurable logic gates with NAND/OR/A̅+B/A+B̅ quadruple functions, which can realize the decoding function of 00–11 in the decoder. The cascade design of the electrically tunable FETs helps to tackle the logic device downscaling and integration dilemmas.