An Adaptive Dictionary Encoding Scheme for SOC Data Buses
As bus lengths on multi-hundred-million transistor SOCs (Systems-On-a-Chip) grow and as inter-wire capacitances of sub-0.10u technologies increase, the resulting high switching capacitances of buses (and interconnects in general) have a non-negligible impact on the power consumption of a whole SOC.I...
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Published in | Proceedings of the conference on Design, automation and test in Europe p. 1059 |
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Main Authors | , , , |
Format | Conference Proceeding |
Language | English |
Published |
Washington, DC, USA
IEEE Computer Society
04.03.2002
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Series | ACM Conferences |
Online Access | Get full text |
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Summary: | As bus lengths on multi-hundred-million transistor SOCs (Systems-On-a-Chip) grow and as inter-wire capacitances of sub-0.10u technologies increase, the resulting high switching capacitances of buses (and interconnects in general) have a non-negligible impact on the power consumption of a whole SOC.In this paper, we address this problem by intoducing our bus encoding technique 'ADES' that minimizes the power consumption of data buses through a dictionary-based encoding technique.We show that our technique saves between 18% and 40% of bus energy compared to the non-encoded cases using a large set of (freely-acesssible) real-world applications.Furthermore, we compare our technique to the best-known data bus encoding techniques to date and it exceeds all of them in energy savings for the same set of applications.The additional hardware effort for our bus en/decoder is thereby very small |
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ISBN: | 0769514715 9780769514710 |
DOI: | 10.5555/882452.874359 |