Power and performance evaluation of globally asynchronous locally synchronous processors

• Published in: Proceedings - International Symposium on Computer Architecture pp. 158 - 168
• Main Authors: Iyer, Anoop, Marculescu, Diana
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 01.05.2002; IEEE
• Series: ACM Conferences
• Subjects: Applied sciences; Electronics; Exact sciences and technology; Hardware > Communication hardware, interfaces and storage > Buses and high-speed links; Hardware > Robustness; Integrated circuits; Integrated circuits by function (including memories and processors); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Asynchronism; Simulation; Superscalar processor
• ISBN: 9780769516059; 076951605X
• ISSN: 1063-6897; 2575-713X
• DOI: 10.5555/545215.545233

Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor die. Asynchronous processor designs do not suffer from this problem since they do not have a global clock. However, a paradigm shift from synchronous to asynchronous is unlikely to happen in the processor industry in the near future. Hence the study of Globally Asynchronous Locally Synchronous (or GALS) systems is relevant. In this paper we use a cycle-accurate simulation environment to study the impact of asynchrony in a superscalar processor architecture. Our results show that as expected, going from a synchronous to a GALS design causes a drop in performance, but elimination of the global clock does not lead to drastic power reductions. From a power perspective, GALS designs are inherently less efficient when compared to synchronous architectures. However, the flexibility offered by the independently controllable local clocks enables the effective use of other energy conservation techniques like dynamic voltage scaling. Our results show that for a 5-clock domain GALS processor, the drop in performance ranges between 5-15%, while power consumption is reduced by 10% on the average. Fine-grained voltage scaling reduces the gap between fully synchronous and GALS implementations, allowing for better power efficiency.