A GHz-class charge recovery logic

• Published in: ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005 pp. 91 - 94
• Main Authors: Sathe, Visvesh S., Papaefthymiou, Marios C., Ziesler, Conrad H.
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 08.08.2005; IEEE
• Series: ACM Conferences
• Subjects: CMOS logic circuits; Dynamic voltage scaling; Energy efficiency; Frequency; Hardware; Logic design; Logic devices; Logic gates; Permission; Pipeline processing; Threshold voltage; resonant systems; energy recovery; adiabatic
• ISBN: 9781595931375; 1595931376
• DOI: 10.1145/1077603.1077627

This paper describes Boost Logic, a logic family which relies on voltage scaling, gate overdrive, and energy recovery, to achieve high energy efficiency at GHz frequencies. The key feature of our design is an energy recovering "boost" stage that provides a high gate overdrive to an aggressively voltage-scaled logic at near-threshold supply voltage. We have evaluated Boost Logic through post-layout simulation of an 8-bit carry-save multiplier in a 0.13μm CMOS process with Vth=340mV. At 1.6GHz and 1.3V supply voltage, the Boost multiplier dissipates 8.11pJ per computation, yielding 68% energy savings over its pipelined, voltage-scaled static CMOS counterpart. Using low Vth devices, the Boost Logic multiplier has been verified to operate at 2GHz with a 1.25V voltage supply and 8.50pJ energy dissipation per cycle