Parity check matrix generation method, data transmission system, encoding device, decoding device, and a parity check matrix generation program

A method is disclosed that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor of a transmission line encoder constructs parity check matrix H from partial matrix H of m rows and k columns on the left side and partial m...

Full description

Saved in:
Bibliographic Details
Main Author Senda, Yuzo
Format Patent
LanguageEnglish
Published 23.10.2012
Online AccessGet full text

Cover

Loading…
Abstract A method is disclosed that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor of a transmission line encoder constructs parity check matrix H from partial matrix H of m rows and k columns on the left side and partial matrix H of m rows and m columns on the right side. The processor generates partial matrix H as a unit matrix. The processor generates partial matrix H to satisfy the conditions that, when any two rows contained in partial matrix H are selected, the two rows have periods that are relatively prime, or when the periods are identical, the two rows have different phases. The processor then joins partial matrix H and partial matrix H to generate parity check matrix H.
AbstractList A method is disclosed that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor of a transmission line encoder constructs parity check matrix H from partial matrix H of m rows and k columns on the left side and partial matrix H of m rows and m columns on the right side. The processor generates partial matrix H as a unit matrix. The processor generates partial matrix H to satisfy the conditions that, when any two rows contained in partial matrix H are selected, the two rows have periods that are relatively prime, or when the periods are identical, the two rows have different phases. The processor then joins partial matrix H and partial matrix H to generate parity check matrix H.
Author Senda, Yuzo
Author_xml – sequence: 1
  givenname: Yuzo
  surname: Senda
  fullname: Senda, Yuzo
BookMark eNqNjbsKAjEQRVNo4esf5gNW8AHLWotiaWEvQzLuBs0kZEZxv8JfdhesLMTqwLkH7tgMODKNzOuI2WsLtiF7hYCa_RNqYsqoPjIE0ia6AhwqgmZkCV6kX6QVpVAAsY3Ocw2OHt5Sl9KXQHaAkH4fpRzrjGFqhhe8Cc0-nBjY707bw_wuCZVY5dxlPRbValOWy2r9R_IGVgFRjA
ContentType Patent
CorporateAuthor NEC Corporation
CorporateAuthor_xml – name: NEC Corporation
DBID EFH
DatabaseName USPTO Issued Patents
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EFH
  name: USPTO Issued Patents
  url: http://www.uspto.gov/patft/index.html
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
ExternalDocumentID 08296618
GroupedDBID EFH
ID FETCH-uspatents_grants_082966183
IEDL.DBID EFH
IngestDate Sun Mar 05 22:31:20 EST 2023
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-uspatents_grants_082966183
OpenAccessLink https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8296618
ParticipantIDs uspatents_grants_08296618
PatentNumber 8296618
PublicationCentury 2000
PublicationDate 20121023
PublicationDateYYYYMMDD 2012-10-23
PublicationDate_xml – month: 10
  year: 2012
  text: 20121023
  day: 23
PublicationDecade 2010
PublicationYear 2012
References Yang et al. "Lowering the error-rate floors of moderate-length high-rate irregular ldpc codes" IEEE international symposium on information theory, New York, NY Jun. 2003 pp. 237 XP010657265.
David J.C. MacKay "Good Error-Correcting Codes Based on Very Sparse Matrices" IEEE Transactions on Information Theory, vol. 45, No. 2, Mar. 2, 1999, pp. 399-431.
Thomas J. Richardson et al. "Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes" IEEE Transactions on Information Theory, vol. 47, No. 2, Feb. 2001, pp. 619-637.
Roca, V. et., al. "Design, Evaluation and Comparison of Four Large Block FEC Codecs, LDPC, LDGM, LDGM Staircase and LDGM Triangle, plus a Reed-Solomom Small Block FEC Codec", Institute National de Recherche en Informatique et en Automatique, No. 5225, Jun. 9, 2004, 26 pages.
Jeongseok Ha et al. "Optimal puncturing of irregular low-density parity-check codes" IEEE International Conference on Communications, New York, NY vol. 5 May 2003 pp. 3110-3114 XP010643019.
Lehmann "Distance properties of irregular ldpc codes" Proceedings 2003 IEEE International, Jun. 29-Jul. 4, 2003, New York, NY, p. 85 XP010657113.
Matsumoto et al. "Irregular Low-Density Parity-Check Code Design Based on Euclidean Geometries" IEICE Transactions on Fundamentals. Jul. 2003, pp. 1820-1834, vol. E86-A, No. 7, Tokyo, Japan XP001174812.
Rosenthal et al. "Constructions of regular and irregular LDPC codes using Ramanujan graphs and ideas from margulis" Proceedings of the 2001 IEEE International Symposium on information theory. Jun. 2001 p. 4 New York, NY XP 010552621.
(2001-168733) 20010600
(2003-296302) 20031000
Johnson et al. "A family of irregular ldpc codes with low encoding complexity" IEEE Communications letters, IEEE Service Center, Piscataway, NJ vol. 7, No. 2, Feb. 2003 XP011066488.
Bjerke et al. (7702986) 20100400
(01/97387) 20011200
(2003-244109) 20030800
Matsumoto et al. "Irregular low-density parity-check code design based on integer lattices" Proceedings 2003 IEEE International., Jun. 29-Jul. 4, 2003, p. 3, New York, NY XP010657031.
Rashidpour et al. "Low-density parity-check codes with simple irregular semi-random parity-check matrix for finite-length applications" Personal, indoor and mobile radio communications, 2003. PIMRC 2003. 14th IEEE Proceedings, Sep. 2003 pp. 439-443 XP 010681634.
Kasai et al. "Detailed representation of irregular ldpc code ensembles and density evolution" IEEE International Symposium on Information Theory, New York, NY Jun. 2003 pp. 121 XP010657149.
Yang et al. "Design of efficiently encodable moderate-length high-rate irregular LDPC codes" Proceedings of the annual conference on communication, control and computing, Oct. 2002 pp. 1415-1424 XP 009042018.
(2003-198383) 20030700
Tian et al. "Construction of irregular LDPC codes with low error floors" IC 2003. 2003 IEEE International, May 11-15, 2003, New York, NY, vol. 4 pp. 3125-3129 XP010643022.
Echard et al. "Irregular/spl pi/-rotation LDPC codes" Globecom 02. IEEE Global Telecommunications Conference, New York, NY vol. 2, Nov. 2002 pp. 1274-1278 XP010636350.
(2003-115768) 20030400
Luby et al. "Improved low-density parity-check codes using irregular graphs and belief propagation" information theory, 1998. Proceedings. Cambridge, MA, p. 117 XP 010297081.
Michael G. Luby et al. "Efficient Erasure Correcting Codes" IEEE Transactions on Information Theory, vol. 47, No. 2, Feb. 2001, pp. 569-584.
Mannoai et al. "Optimized irregular gallager codes for OFDM transmission" Personal, indoor and mobile radio communications, 2002. vol. 1 pp. 222-226 XP010614219.
Liuguo et al. "Modified belief-propagation algorithm for decoding of irregular low-density parity-check codes" Electronics letters, vol. 38, No. 24, Nov. 2002 pp. 1551-1553 XP 006019345.
References_xml – year: 20011200
  ident: 01/97387
– year: 20010600
  ident: 2001-168733
– year: 20030400
  ident: 2003-115768
– year: 20031000
  ident: 2003-296302
– year: 20100400
  ident: 7702986
  contributor:
    fullname: Bjerke et al.
– year: 20030800
  ident: 2003-244109
– year: 20030700
  ident: 2003-198383
Score 2.8655858
Snippet A method is disclosed that allows the easy generation of low-density parity-check codes that can realize superior error-correcting characteristics. A processor...
SourceID uspatents
SourceType Open Access Repository
Title Parity check matrix generation method, data transmission system, encoding device, decoding device, and a parity check matrix generation program
URI https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8296618
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1NS8QwEB12F0E9KSquX8zB40b7lW08y5biQXpQ2JskTdaDblpsF_0X_mVn2mURwT0FJiVNJyRvJnl9AbhOreUkmTLVWMYiCRdSaE2Jq3SGAEpFSVp2LN_Haf6cPMzlfAD55l-YJU0jUVNfmptVU7dVR66k5b0feNGLP7NGoGf1gU__Xmlb2MWtiihwD9UQhipgat8sy_dhl5qgkM23zS_QyA5gp-ishzBw_gi-C80XxSF5qXzDJUvjf-Frp_rMzsH-LucJMmcTW4YQGgLey8JebXmCrDnJUIPW8fymR90fg_YWNdbbX7SmZB0DZrOn-1xsev9CZi6C9VfGJzDylXengCkf3RkKchiokzAw07vE2tKoqIylVXIM43-bOdtSdw57FBtEvExH8QWM2o-VuyT8bc1V59wfceCTKA
link.rule.ids 230,309,783,805,888,64367
linkProvider USPTO
linkToPdf http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3JTsMwEB2VglhOIEAt6xw4NtAsTsIZiMKiKgeQequc2OUAdSKSCv6CX2bGqSqERE-WxpaXsew3Y4-fAS4ipdhJJk_VF74TuFPhSEmOq9A5AVTsBVFho3xHYfoSPIzFuAPp8i3MjJaRU1Ff6st5XTWlDa6k7b2deKclf2aOQMPsA5_mvZQqU9Or2CPD3Y3XYJ0wNrQuWZLuwBZVQkabaepfsJHswkZmpXvQ0WYfvjPJX8Uh6al4wxmT43_hq-V9ZvVg-5vzADlqExsGEZoEPs3Clm95gMw6yWCDSvMKp6L6j0AahRKr1Q0tgrIOAJO755vUWfZ-QmJOhotx-ofQNaXRPcCIL-9yMnMYqgN3mIfXgVJFHnuFL1Qs-tD_t5qjFXnnsJndJpOn-9HjMWyToeDxnu35J9BtPub6lMC4yc-snn8AyxGWJQ
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Parity+check+matrix+generation+method%2C+data+transmission+system%2C+encoding+device%2C+decoding+device%2C+and+a+parity+check+matrix+generation+program&rft.inventor=Senda%2C+Yuzo&rft.number=8296618&rft.date=2012-10-23&rft.externalDBID=n%2Fa&rft.externalDocID=08296618