Stressed barrier plug slot contact structure for transistor performance enhancement
A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barri...
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Format | Patent |
Language | English |
Published |
02.10.2012
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Online Access | Get full text |
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Abstract | A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices. |
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AbstractList | A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices. |
Author | Chikarmane, Vinay B Fischer, Kevin J Peterson, Brennan L |
Author_xml | – sequence: 1 givenname: Kevin J surname: Fischer fullname: Fischer, Kevin J – sequence: 2 givenname: Vinay B surname: Chikarmane fullname: Chikarmane, Vinay B – sequence: 3 givenname: Brennan L surname: Peterson fullname: Peterson, Brennan L |
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References | Tamura et al. (2006/0220113) 20061000 Furukawa et al. (7102201) 20060900 Cheng et al. (2005/0110082) 20050500 Chuang et al. (2008/0296691) 20081200 Yamada et al. (2006/0131662) 20060600 Gerhardt et al. (7964970) 20110600 Drewery et al. (6790773) 20040900 Intel Corporation Office Action for U.S. Appl. No. 13/028,097 mailed May 18, 2011. Fisher et al. (7719062) 20100500 Sandhu et al. (6881667) 20050400 Tamaru (2005/0194637) 20050900 Kang et al. (7183207) 20070200 Intel Corporation Office Action for U.S. Appl. No. 11/648,098 mailed Jan. 14, 2010. Bryant et al. (7227205) 20070600 Intel Corporation Notice of Allowance for U.S. Appl. No. 11/648,098 mailed Feb. 3, 2011. Tamura et al. (7649232) 20100100 Intel Corporation Office Action for U.S. Appl. No. 11/648,098 mailed Jun. 24, 2009. Intel Corporation Office Action for U.S. Appl. No. 11/648,098 mailed Jul. 15, 2010. Yoon et al. (2007/0026712) 20070200 Intel Corporation Office Action for U.S. Appl. No. 11/648,098 mailed Dec. 22, 2010. Intel Corporation Notice of Allowance for U.S. Appl. No. 11/647,977 mailed Jan. 6, 2010. Wei et al. (2007/0228482) 20071000 Kanarsky et al. (2008/0083955) 20080400 Ting et al. (7288822) 20071000 Kawakita (2008/0023772) 20080100 Murthy et al. (6621131) 20030900 Merchant et al. (6982226) 20060100 Motoyama (2003/0075752) 20030400 Ting et al. (7410875) 20080800 Dawson et al. (6087706) 20000700 Intel Corporation Notice of Allowance for U.S. Appl. No. 13/028,097 mailed Oct. 19, 2011. Intel Corporation Office Action for U.S. Appl. No. 11/647,977 mailed Jun. 22, 2009. |
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