Semiconductor memory device

Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells u...

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Bibliographic Details
Main Authors Hur, Hwang, Do, Chang-Ho, Ko, Jae-Bum, Chung, Jin-Il
Format Patent
LanguageEnglish
Published 17.07.2012
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Summary:Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.