High frequency power amplifier and operating method thereof
A high-frequency power amplifier which can reduce a variation of power gain due to the dependence on gate length of a power amplification field effect transistor is provided. The high-frequency power amplifier comprises, over a semiconductor chip, a bias control circuit, a bias transistor and an amp...
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Format | Patent |
Language | English |
Published |
22.05.2012
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Abstract | A high-frequency power amplifier which can reduce a variation of power gain due to the dependence on gate length of a power amplification field effect transistor is provided. The high-frequency power amplifier comprises, over a semiconductor chip, a bias control circuit, a bias transistor and an amplification transistor which are coupled so as to configure a current mirror circuit, and a gate length monitor circuit comprising a replicating transistor. The amplification transistor amplifies an RF signal and a bias current of the bias control circuit is supplied to the bias transistor. The transistors are fabricated by the same semiconductor manufacturing process, and have the same variation of gate length. The gate length monitor circuit generates a detection voltage depending on the gate length. According to the detection voltage, the bias control circuit controls the bias current, thereby compensating the gate length dependence of transconductance of the amplification transistor. |
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AbstractList | A high-frequency power amplifier which can reduce a variation of power gain due to the dependence on gate length of a power amplification field effect transistor is provided. The high-frequency power amplifier comprises, over a semiconductor chip, a bias control circuit, a bias transistor and an amplification transistor which are coupled so as to configure a current mirror circuit, and a gate length monitor circuit comprising a replicating transistor. The amplification transistor amplifies an RF signal and a bias current of the bias control circuit is supplied to the bias transistor. The transistors are fabricated by the same semiconductor manufacturing process, and have the same variation of gate length. The gate length monitor circuit generates a detection voltage depending on the gate length. According to the detection voltage, the bias control circuit controls the bias current, thereby compensating the gate length dependence of transconductance of the amplification transistor. |
Author | Hayashi, Norio Hase, Masatoshi Morisawa, Fuminori Ohta, Ikuma Tsutsui, Takayuki |
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References | (2005-20518) 20050100 Tsurumaki et al. (7443245) 20081000 Matsunaga et al. (6759906) 20040700 Tsurumaki et al. (2009/0072906) 20090300 Tsutsui et al. (7123095) 20061000 Tsurumaki et al. (2005/0083129) 20050400 Akamine et al. (2004/0108902) 20040600 Tsurumaki et al. (2008/0068086) 20080300 (2005-150917) 20050600 (2005-123861) 20050500 Ishikawa et al. (7501896) 20090300 Tsutsui et al. (2007/0008037) 20070100 |
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