Methods of fabricating integrated circuit devices including strained channel regions and related devices

A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the substrate. P-type source/drain regions are epitaxially grown on opposite sides of the first gate pattern in the...

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Main Authors Kim, Ki-chul, Lee, Ho, Lee, Jung-deog
Format Patent
LanguageEnglish
Published 27.12.2011
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Abstract A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the substrate. P-type source/drain regions are epitaxially grown on opposite sides of the first gate pattern in the PMOS region to exert compressive stress on a first channel region therebetween adjacent the first gate pattern. N-type source/drain regions are epitaxially grown on opposite sides of the second gate pattern in the NMOS region to exert tensile stress on a second channel region therebetween adjacent the second gate pattern. Related devices are also discussed.
AbstractList A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the substrate. P-type source/drain regions are epitaxially grown on opposite sides of the first gate pattern in the PMOS region to exert compressive stress on a first channel region therebetween adjacent the first gate pattern. N-type source/drain regions are epitaxially grown on opposite sides of the second gate pattern in the NMOS region to exert tensile stress on a second channel region therebetween adjacent the second gate pattern. Related devices are also discussed.
Author Lee, Ho
Lee, Jung-deog
Kim, Ki-chul
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