Semiconductor integrated circuit
During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase compa...
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Format | Patent |
Language | English |
Published |
18.10.2011
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Online Access | Get full text |
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Abstract | During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator. |
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AbstractList | During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator. |
Author | Sumita, Masaya |
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References | Treadway (3610954) 19711000 Hatchett et al. (4378509) 19830300 Chien (6154096) 20001100 Ooishi et al. (6166990) 20001200 Johnson (5297092) 19940300 Ferraiolo et al. (5757238) 19980500 Japanese Office Action, with English Translation, issued in Japanese Patent Application No. JP 2003-151943, mailed Jun. 26, 2007. Arimoto et al. (6400625) 20020600 English Translation of Chinese Office Action issued in Chinese Patent Application No. CN 200510068135.2, dated Apr. 4, 2008. Machida (5457788) 19951000 (63-119318) 19880500 (2000-224035) 20000800 (9-130240) 19970500 (2003-333698) 20031100 Volk et al. (4829258) 19890500 Lofgren et al. (4922141) 19900500 Lin (6407601) 20020600 Pawlowski (5905996) 19990500 Japanese Office Action, with English Translation, issued in Japanese Patent Application No. JP 2007-218055, mailed Mar. 18, 2008. Young et al. (5412349) 19950500 Watanabe (2006/0156119) 20060700 (7-262781) 19951000 (01-099433) 19990400 |
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Snippet | During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion... |
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