Branch prediction within a multithreaded processor

A branch prediction mechanism within a multithreaded processor having hardware scheduling logic uses a shared global history table which is indexed by respective branch history registers for each program thread. Different mappings are used between preceding branch behavior and the prediction value s...

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Bibliographic Details
Main Authors Vasekin, Vladimir, Biles, Stuart David, Levdik, Yuri, Kapustin, Andrei
Format Patent
LanguageEnglish
Published 25.01.2011
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Summary:A branch prediction mechanism within a multithreaded processor having hardware scheduling logic uses a shared global history table which is indexed by respective branch history registers for each program thread. Different mappings are used between preceding branch behavior and the prediction value stored within respective branch history registers . These different mappings may be provided by inverters placed into the shift in paths for the branch history registers or by adders or in some other way. The different mappings help to equalise the probability of use of the particular storage locations within the global history table such that the plurality of program threads are not competing excessively for the same storage locations corresponding to the more commonly occurring patterns of preceding branch behavior.