Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes

• Main Authors: Daly, Jr, George W, Fields, Jr, James S, Guthrie, Guy L, Starke, William J, Stuecheli, Jeffrey A
• Format: Patent
• Language: English
• Published: 25.05.2010

A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.