Multilayer passive circuit topology

• Main Authors: Goyette, William R, Winter, Frank B, Johnston, Eric C, Patel, Hardik
• Format: Patent
• Language: English
• Published: 25.05.2010

A multilayer passive circuit topology is disclosed. In one embodiment, a multilayer circuit is provided. The multilayer circuit comprises a multilayer inductor comprising a first set of parallel conductive traces formed on a first layer, a second set of parallel conductive traces formed on a second layer spaced apart from the first layer; and a plurality of vias that connect respective parallel conductive traces from the first and second layer to form inductor windings. The multilayer circuit further comprises a multilayer capacitor connected to an end of the inductor by a coupling via, the capacitor comprising a first conductive plate and a second conductive plate being spaced apart from one another and being formed on different layers.