Performance monitors (PMs) for measuring performance in a system and providing a record of transactions performed
Performance monitors (PMs) are provided in a system to identify the execution time for data being transferred within the system and determine operation parameters of the system based on the rate data is transferred. The operation parameters are then used to configure hardware within the system. The...
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Format | Patent |
Language | English |
Published |
18.05.2010
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Abstract | Performance monitors (PMs) are provided in a system to identify the execution time for data being transferred within the system and determine operation parameters of the system based on the rate data is transferred. The operation parameters are then used to configure hardware within the system. The PMs can provide a histogram of the transactions usable to evaluate system performance. The PMs can provide a time line diagram of the transactions to show the specific order the transactions occurred. The PMs can be provided in a multi-port memory controller (MPMC) to monitor the speed of read and write transactions from the MPMC ports, and used to configure logic within the MPMC to maximize the rate of data flow. |
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AbstractList | Performance monitors (PMs) are provided in a system to identify the execution time for data being transferred within the system and determine operation parameters of the system based on the rate data is transferred. The operation parameters are then used to configure hardware within the system. The PMs can provide a histogram of the transactions usable to evaluate system performance. The PMs can provide a time line diagram of the transactions to show the specific order the transactions occurred. The PMs can be provided in a multi-port memory controller (MPMC) to monitor the speed of read and write transactions from the MPMC ports, and used to configure logic within the MPMC to maximize the rate of data flow. |
Author | Baxter, Glenn A Lilley, Jennifer R |
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CorporateAuthor | XILINX, Inc |
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References | Shaw et al. (4349870) 19820900 Douglass et al. (6662285) 20031200 Gerard (2006/0047992) 20060300 Furtek et al. (7225301) 20070500 Xilinx, Inc., "Gigabit System Reference Design", XAPP536, Jun. 3, 2004, pp. 1-51, v1.1, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. U.S. Appl. No. 11/706,556, filed Feb. 14, 2007 Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124. Lattimore et al. (5870349) 19990200 Georg et al. (4511964) 19850400 Truchard et al. (6983393) 20060100 Matsuzaki et al. (7120761) 20061000 Pani et al. (6329839) 20011200 Chen et al. (5761478) 19980600 Brock et al. (6601149) 20030700 Nelson et al. (5889987) 19990300 U.S. Appl. No. 11/707,175, filed Feb. 14, 2007 Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124. Van der Wal (6567564) 20030500 Muret et al. (6792458) 20040900 Xilinx, Inc., "High Performance Multi-Port Memory Controller", XAPP535, Dec. 10, 2004, pp. 1-190, v1.1, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Hatley (6871312) 20050300 Gach et al. (4912632) 19900300 U.S. Appl. No. 11/707,108, filed Feb. 14, 2007 Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124. Gerard (7287196) 20071000 Suzuki et al. (6754786) 20040600 U.S. Appl. No. 11/706,610, filed Feb. 14, 2007 Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124. Dao et al. (7076595) 20060700 Leijten (7308540) 20071200 Xilinx, Inc., "Multi Port Memory Controller-MPMC2", Oct. 20, 2006, 2 pages, v.1.7, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Brelet (6353332) 20020300 Baxter et al. (7260688) 20070800 Agrawal et al. (5768500) 19980600 Shrader et al. (2005/0060456) 20050300 Jenkins, IV (7308564) 20071200 Lilley (7454546) 20081100 Marisetty (5666521) 19970900 Peck et al. (2003/0036875) 20030200 Jones (5804986) 19980900 Gross et al. (7020802) 20060300 Matsuno et al. (5651112) 19970700 Baxter, Glenn A. et al., Method and Apparatus for Controlling Access to Memory Circuitry, U.S. Appl. No. 10/84,967, filed Apr. 15, 2004, pp. 1-76, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Borrelli, Christopher, J. et al., "Method and Apparatus for Communicating Data Between a Network Transceiver and Memory Circuitry", U.S. Appl. No. 10/824,715, filed Apr. 15, 2004, pp. 1-75, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Silvkoff et al. (6601130) 20030700 Baxter, Glenn A. et al., "Method and Apparatus for Controlling Direct Access to Memory Circuitry", U.S. Appl. No. 10/824,713, filed Apr. 15, 2004, pp. 1-75, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Carr et al. (6333935) 20011200 Fernandez et al. (7072800) 20060700 Cirne (2004/0075690) 20040400 Lilley, Jennifer R. et al., "Architecture for Dynamically Reprogrammable Arbitration Using Memory", U.S. Appl. No. 11/341,033, filed Jan. 27, 2006, pp. 1-23, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Pang et al. (6373779) 20020400 |
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