Variable signal delaying circuit, quadrature frequency converter and radio frequency tuner
A variable signal delaying circuit comprising an analog delay line having a control input for controlling the variable delay. A phase detector compares the input and output signals of the delaying circuit and supplies an output signal to a charge pump and integrator. A pulse stream generating arrang...
Saved in:
Main Authors | , , |
---|---|
Format | Patent |
Language | English |
Published |
20.10.2009
|
Online Access | Get full text |
Cover
Loading…
Abstract | A variable signal delaying circuit comprising an analog delay line having a control input for controlling the variable delay. A phase detector compares the input and output signals of the delaying circuit and supplies an output signal to a charge pump and integrator. A pulse stream generating arrangement produces pulse streams of different pulse widths and pulse control logic controls a selector for selecting any one of the pulse streams. In a first mode of operation, the control logic monitors the charge pump/filter output and selects the pulse stream which minimizes change in the output. The selection is fixed and the output of the charge pump/filter is then supplied as a correction signal to the control input of the analog delay line. Such an arrangement may be used to maintain minimum phase imbalance in I and Q signal paths of a quadrature frequency converter. |
---|---|
AbstractList | A variable signal delaying circuit comprising an analog delay line having a control input for controlling the variable delay. A phase detector compares the input and output signals of the delaying circuit and supplies an output signal to a charge pump and integrator. A pulse stream generating arrangement produces pulse streams of different pulse widths and pulse control logic controls a selector for selecting any one of the pulse streams. In a first mode of operation, the control logic monitors the charge pump/filter output and selects the pulse stream which minimizes change in the output. The selection is fixed and the output of the charge pump/filter is then supplied as a correction signal to the control input of the analog delay line. Such an arrangement may be used to maintain minimum phase imbalance in I and Q signal paths of a quadrature frequency converter. |
Author | Sawyer, David Albert Cowley, Nicholas Paul Isaac, Ali |
Author_xml | – sequence: 1 givenname: Ali surname: Isaac fullname: Isaac, Ali – sequence: 2 givenname: Nicholas Paul surname: Cowley fullname: Cowley, Nicholas Paul – sequence: 3 givenname: David Albert surname: Sawyer fullname: Sawyer, David Albert |
BookMark | eNqNyj0KAjEQQOEUWvh3hzmAwmJg9wCieACxsJExmQ2BMOtOZoS9vQgWllZf8d7SzXhgWrjbFSXjoxDUnBgLRCo4ZU4QsgTLuoXRMAqqCUEvNBpxmCAM_CJREkCOIBjz8FPVmGTt5j2WSpuvKwen4-Vw3ll9ohJrvSfBD03XNq33e__H8gZsDj5d |
ContentType | Patent |
CorporateAuthor | Intel Corporation |
CorporateAuthor_xml | – name: Intel Corporation |
DBID | EFH |
DatabaseName | USPTO Issued Patents |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EFH name: USPTO Issued Patents url: http://www.uspto.gov/patft/index.html sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
ExternalDocumentID | 07606332 |
GroupedDBID | EFH |
ID | FETCH-uspatents_grants_076063323 |
IEDL.DBID | EFH |
IngestDate | Sun Mar 05 22:32:16 EST 2023 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-uspatents_grants_076063323 |
OpenAccessLink | https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7606332 |
ParticipantIDs | uspatents_grants_07606332 |
PatentNumber | 7606332 |
PublicationCentury | 2000 |
PublicationDate | 20091020 |
PublicationDateYYYYMMDD | 2009-10-20 |
PublicationDate_xml | – month: 10 year: 2009 text: 20091020 day: 20 |
PublicationDecade | 2000 |
PublicationYear | 2009 |
References | Cho (6518807) 20030200 Joy et al. (7245117) 20070700 Kasperkovitz (2002/0065057) 20020500 Sawyer et al. (7327179) 20080200 Isaac et al. (2006/0281432) 20061200 Ooishi et al. (2002/0024366) 20020200 (6097755) 19940400 Lee (2005/0285643) 20051200 Lee (2005/0127964) 20050600 Roth et al. (6519305) 20030200 (4025245) 19920100 |
References_xml | – year: 19920100 ident: 4025245 – year: 20030200 ident: 6518807 contributor: fullname: Cho – year: 20050600 ident: 2005/0127964 contributor: fullname: Lee – year: 20080200 ident: 7327179 contributor: fullname: Sawyer et al. – year: 19940400 ident: 6097755 – year: 20061200 ident: 2006/0281432 contributor: fullname: Isaac et al. – year: 20020200 ident: 2002/0024366 contributor: fullname: Ooishi et al. – year: 20020500 ident: 2002/0065057 contributor: fullname: Kasperkovitz – year: 20051200 ident: 2005/0285643 contributor: fullname: Lee – year: 20070700 ident: 7245117 contributor: fullname: Joy et al. – year: 20030200 ident: 6519305 contributor: fullname: Roth et al. |
Score | 2.7500098 |
Snippet | A variable signal delaying circuit comprising an analog delay line having a control input for controlling the variable delay. A phase detector compares the... |
SourceID | uspatents |
SourceType | Open Access Repository |
Title | Variable signal delaying circuit, quadrature frequency converter and radio frequency tuner |
URI | https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7606332 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8QwEB7WRdA9KSquL3LwaLTbh03Oy5YiKHtQWbwsSZtKYW3XNEX89860suxFrxkYhoR5Jd98Abgu6I_o2JM8CrTkoa8FV9JHvxLSC5WMdFjQPeTj0336Ej4sosUA0s0szAe6EV-jLc1t26xd3YErMbz3B8978mfiCKyIfeCrWtUqn-fFXYyVeBBgMN4RHkH7Zkk6gj1UgSVb5ZqtpJEcwO68Wz2EgamO4O0V21IaVGKEmVArRvyMNGTEstJmbelu2Ger8p7jmBW2xzh_sw4XTsBLhk0_syov6y2paytjj4Els-dpyjeGLN8tAVyW3q_BwQkMsdE3p8DyWGstjFaRDEIttJKZUNgOaQwC0kwmYxj_qebsH9k57HdvIBhxfe8Chs625hJTqdNX3T79AHAPgQc |
link.rule.ids | 230,309,783,805,888,64367 |
linkProvider | USPTO |
linkToPdf | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8QwEB6WVXycFBXXZw4ejXa37bY5q6W-lh5UFi8laVMp7LZrmiL-eyepLHvRawLDkDAz-ZJvvgBcFOaP6MBh1HcFo95IhJSzEcZVyByPM194hbmHfJ6M41fvYepPexAve2HmGEZ0gb40V22z0LUlV2J67zaeduLPRiOwMuoDX9Ws5nmSF9cBnsRdF5PxGtbYsYVkUbwNm2gED22VblbKRrQD64kd3YWerPbg_Q2BqWlVIoY1wWfEKDSaNiOSlSprS31JPluedyrHpFAdy_mbWGa4oV4ShP1E8bysV2Z1W0m1DyS6e7mJ6dKR9EMZikvq_LrsHkAfob48BJIHQohQCu4z1xOh4CwLOQIigWmAyeFwAIM_zRz9M3cOG8ltlD7dTx6PYcs-iGD6HTkn0NeqladYV7U4s0v2A-p2hAQ |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Variable+signal+delaying+circuit%2C+quadrature+frequency+converter+and+radio+frequency+tuner&rft.inventor=Isaac%2C+Ali&rft.inventor=Cowley%2C+Nicholas+Paul&rft.inventor=Sawyer%2C+David+Albert&rft.number=7606332&rft.date=2009-10-20&rft.externalDBID=n%2Fa&rft.externalDocID=07606332 |