Wafer with improved sawing loops

In a wafer with chips and elongate separating zones between the chips, each chip comprises at least one sawing loop, which sawing loop comprises two protecting strips projecting from a planar protecting layer of the chip, wherein said protecting strips are widened by means of wider strip portions wh...

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Main Author Heimo, Scheucher
Format Patent
LanguageEnglish
Published 18.08.2009
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Abstract In a wafer with chips and elongate separating zones between the chips, each chip comprises at least one sawing loop, which sawing loop comprises two protecting strips projecting from a planar protecting layer of the chip, wherein said protecting strips are widened by means of wider strip portions where they emerge from the planar protecting layer, and wherein the protecting strips and the planar protecting layer are provided with weak spots serving as envisaged breakage points.
AbstractList In a wafer with chips and elongate separating zones between the chips, each chip comprises at least one sawing loop, which sawing loop comprises two protecting strips projecting from a planar protecting layer of the chip, wherein said protecting strips are widened by means of wider strip portions where they emerge from the planar protecting layer, and wherein the protecting strips and the planar protecting layer are provided with weak spots serving as envisaged breakage points.
Author Heimo, Scheucher
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References Tada (6465872) 20021000
Bergler et al. (2002/0016033) 20020200
Patent Abstracts of Japan. Publication No. 10-163522; Application No. 08-319286 titled, "Manufacture of LED Array," Jun. 19, 1998.
"PCT International Search Report with mailing date, Feb. 6, 2006, (International Application No. PCT/ IB2005/052428)".
Guthrie et al. (6492247) 20021200
(10 164522) 19980900
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Title Wafer with improved sawing loops
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