Mechanism for read-only memory built-in self-test

In one embodiment, a method for on-die read only memory (ROM) built-in self-test (BIST) is disclosed. The method comprises testing odd word line entries of a read-only memory (ROM) array by performing two passes through the ROM array to test each odd word line entry for static and delay faults, test...

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Bibliographic Details
Main Authors Chhabra, Pawan, Thomas, Tessil
Format Patent
LanguageEnglish
Published 06.01.2009
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Summary:In one embodiment, a method for on-die read only memory (ROM) built-in self-test (BIST) is disclosed. The method comprises testing odd word line entries of a read-only memory (ROM) array by performing two passes through the ROM array to test each odd word line entry for static and delay faults, testing even word line entries of the ROM array by performing two passes through the ROM array to test each even word line entry for static and delay faults, and testing each entry of the ROM array for static faults masked by dynamic faults by performing two passes through the ROM array. Other embodiments are also described.