System for testing DUT and tester for use therewith

A tester configured to stack with at least one other tester to provide a test system for simultaneously testing a number of devices in parallel on different testers, or testing a device having more pins than can be accommodated by a single tester. The tester includes a test site with a number of pin...

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Bibliographic Details
Main Authors Magliocco, Paul, Wakefield, Ray, Trudeau, Paul G
Format Patent
LanguageEnglish
Published 10.06.2008
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Abstract A tester configured to stack with at least one other tester to provide a test system for simultaneously testing a number of devices in parallel on different testers, or testing a device having more pins than can be accommodated by a single tester. The tester includes a test site with a number of pin electronics channels, an interface for interfacing with the device, and a computer for interfacing with a host computer in the test system. The testers can be fastened directly to one another or to a common frame. Preferably, the interface enables a single device board to simultaneously engage interfaces on multiple testers. More preferably, the interface extends from a top surface of the tester to engage the device board. Vents in top and front surfaces of an enclosure enables movement of air to cool components of the tester without interference from testers on either side or a back of the enclosure.
AbstractList A tester configured to stack with at least one other tester to provide a test system for simultaneously testing a number of devices in parallel on different testers, or testing a device having more pins than can be accommodated by a single tester. The tester includes a test site with a number of pin electronics channels, an interface for interfacing with the device, and a computer for interfacing with a host computer in the test system. The testers can be fastened directly to one another or to a common frame. Preferably, the interface enables a single device board to simultaneously engage interfaces on multiple testers. More preferably, the interface extends from a top surface of the tester to engage the device board. Vents in top and front surfaces of an enclosure enables movement of air to cool components of the tester without interference from testers on either side or a back of the enclosure.
Author Trudeau, Paul G
Magliocco, Paul
Wakefield, Ray
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References Organ et al. (6449741) 20020900
Harns (4460997) 19840700
Okayasu (6157200) 20001200
Ueda (5053698) 19911000
Botka (5550466) 19960800
Sakai (5650732) 19970700
Yamada et al. (5497079) 19960300
Hanners et al. (6040691) 20000300
Arkin et al. (5951705) 19990900
Fujimoto (5952842) 19990900
Melgaard et al. (4729246) 19880300
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