Attachment of integrated circuit structures and other substrates to substrates with vias

Vias (B) are formed in a surface of a substrate. At least portions of contact pads are located in the vias. Contact pads of an integrated circuit structure are inserted into the vias and attached to the contact pads of the substrate. The vias provide a strong, reliable mechanical and electrical conn...

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Main Authors Savastiouk, Sergey, Kao, Sam
Format Patent
LanguageEnglish
Published 10.07.2007
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Abstract Vias (B) are formed in a surface of a substrate. At least portions of contact pads are located in the vias. Contact pads of an integrated circuit structure are inserted into the vias and attached to the contact pads of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad in the substrate but also a surrounding region. Solder wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers, with the top layer being more solder wettable than the bottom layer and the top layer covering only a portion of the bottom layer.
AbstractList Vias (B) are formed in a surface of a substrate. At least portions of contact pads are located in the vias. Contact pads of an integrated circuit structure are inserted into the vias and attached to the contact pads of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad in the substrate but also a surrounding region. Solder wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers, with the top layer being more solder wettable than the bottom layer and the top layer covering only a portion of the bottom layer.
Author Kao, Sam
Savastiouk, Sergey
Author_xml – sequence: 1
  givenname: Sergey
  surname: Savastiouk
  fullname: Savastiouk, Sergey
– sequence: 2
  givenname: Sam
  surname: Kao
  fullname: Kao, Sam
BookMark eNqNjbsKAjEQRVNo4WP_YX5A8L21iOIHWNhJzM5uAutEMjf6-0awsLQ6nMuBOzYDicIjc9kB1vk7Cyi2FATcJQtuyIXkcgApUnbIiZWsNBThOZHmW9lLp4T4a68AT89gdWqGre2Vqy8nho6H8_40y_oopUCv5eiDeb1cL7b1ZvVH8gYOIz3u
ContentType Patent
CorporateAuthor Tru-Si Technologies, Inc
CorporateAuthor_xml – name: Tru-Si Technologies, Inc
DBID EFH
DatabaseName USPTO Issued Patents
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EFH
  name: USPTO Issued Patents
  url: http://www.uspto.gov/patft/index.html
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
ExternalDocumentID 07241675
GroupedDBID EFH
ID FETCH-uspatents_grants_072416753
IEDL.DBID EFH
IngestDate Sun Mar 05 22:31:31 EST 2023
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-uspatents_grants_072416753
OpenAccessLink https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7241675
ParticipantIDs uspatents_grants_07241675
PatentNumber 7241675
PublicationCentury 2000
PublicationDate 20070710
PublicationDateYYYYMMDD 2007-07-10
PublicationDate_xml – month: 07
  year: 2007
  text: 20070710
  day: 10
PublicationDecade 2000
PublicationYear 2007
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References_xml – year: 20010600
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– year: 20030300
  ident: 2003/0047798
  contributor:
    fullname: Halahan
– year: 20010100
  ident: 6175158
  contributor:
    fullname: Degani et al.
– year: 20031200
  ident: 6661088
  contributor:
    fullname: Yoda et al.
– year: 20040500
  ident: 2004/0087057
  contributor:
    fullname: Wang et al.
– year: 20010900
  ident: 2001/0019178
  contributor:
    fullname: Brofman et al.
– year: 20001200
  ident: 6163456
  contributor:
    fullname: Suzuki et al.
– year: 20021200
  ident: 6498381
  contributor:
    fullname: Halahan et al.
– year: 19970200
  ident: 195 31 158
– year: 20031200
  ident: 2003/0226254
  contributor:
    fullname: Koning et al.
– year: 19970300
  ident: 5611140
  contributor:
    fullname: Kulesza et al.
– year: 20021100
  ident: 2002/0175421
  contributor:
    fullname: Kimura
– year: 20001200
  ident: 6165885
  contributor:
    fullname: Gaynes et al.
– year: 20021200
  ident: 6498074
  contributor:
    fullname: Siniaguine et al.
– year: 19950200
  ident: 5391514
  contributor:
    fullname: Gall et al.
– year: 20011100
  ident: 6322903
  contributor:
    fullname: Siniaguine et al.
– year: 19960900
  ident: 08-236579
– year: 20031000
  ident: 2003/0199123
  contributor:
    fullname: Siniaguine
– year: 19860900
  ident: 0 193 128
– year: 20020300
  ident: 2002/0036340
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– year: 20010200
  ident: 6190940
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    fullname: DeFelice et al.
– year: 20030500
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– year: 20031100
  ident: 2003/0211720
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    fullname: Huang et al.
– year: 20020400
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    fullname: Yanagida
– year: 20030600
  ident: 2003/0116859
  contributor:
    fullname: Hashimoto
– year: 20020600
  ident: 6399178
  contributor:
    fullname: Chung
– year: 20050600
  ident: 6903443
  contributor:
    fullname: Farnworth et al.
– year: 20020600
  ident: 2002/0074637
  contributor:
    fullname: McFarland
Score 2.6828897
Snippet Vias (B) are formed in a surface of a substrate. At least portions of contact pads are located in the vias. Contact pads of an integrated circuit structure are...
SourceID uspatents
SourceType Open Access Repository
Title Attachment of integrated circuit structures and other substrates to substrates with vias
URI https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7241675
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3PS8MwFH5sQ9CdFBXnVN7Ba7SStKtHkZUiKDso9CZJk2JB22HS-e_7kmrZRU8hCTy-JCTvB-99AbhcaCNUygUTVcKZiHXClLrlzAjSZlJFXIcK78enJH8RD0VcjCAfamE-6BqxNWGxV51duzYkV9Lz3h8868mfPUdg49kHvpr3VuqVrq4XpIrI-B3DOI18atcyy6ewSyLIZGuc3VIa2T7srMLoAYxMcwjFnXOyfPPROGwrHHgaNJb1Z9nVDnsu144cYCT_HkNtFFrCGBhkLbp2u-cjqLippT0CzJbP9zkbYLySYN9EP3D5MUzIzTcngMpoLkQlyaDQooq5lJruW2pUXPrvpcwMZn-KOf1nbg57v_HIm-gMJrQUc06K1KmLsEvfnQCBOw
link.rule.ids 230,309,786,808,891,64396
linkProvider USPTO
linkToPdf http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV07T8MwED6VgnhMIEC0vDywGoLspO2IoFF4VRlAylbZsSMi0aTCDvx9zg5EXWCybEun8_O7O_k-A1yMlOZyzDjlRcQoD1VEpZwwqjmimZABUz7D-3kWJa_8IQuzHiRdLswCjxFdoi7msjFLW_vHlXi9twtPW_JnxxFYOfaBr-q9FipVxdUIoQiN3zVYdxjr9vo0TnZgC4Wg0VZZswIb8S5spL51D3q62ofsxlqRv7l4HKkL0jE1KJKXH3lTWtKyuTboAhP08InPjiIGtfQcsobYerXmYqjksxTmAEg8fblNaKfGHAW7IvhRmB1CHx19fQREasU4LwSaFIoXIRNC4Ykbaxnm7oMpPYDBn2KG__Sdw2Z6F8-f7mePx7D9G5y8Dk6gj6PSp4iqVp75CfsGGMyENw
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Attachment+of+integrated+circuit+structures+and+other+substrates+to+substrates+with+vias&rft.inventor=Savastiouk%2C+Sergey&rft.inventor=Kao%2C+Sam&rft.number=7241675&rft.date=2007-07-10&rft.externalDBID=n%2Fa&rft.externalDocID=07241675