Error correction method, apparatus and program product
a An error correction apparatus includes: an error correction circuit for performing a data error correction based on a first error correction algorithm selected from among a plurality of error correction algorithms having different correction strengths; an error determination unit for using the fir...
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Format | Patent |
Language | English |
Published |
05.12.2006
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Online Access | Get full text |
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Abstract | a An error correction apparatus includes: an error correction circuit for performing a data error correction based on a first error correction algorithm selected from among a plurality of error correction algorithms having different correction strengths; an error determination unit for using the first error correction algorithm to detect that the data error correction has been disabled; and a computer for selecting a second error correction algorithm from the plurality of error correction algorithms, and for controlling the error correction circuit to use the second error correction algorithm to perform the error correction for data for which it has been determined that the first error correction algorithm is not capable of correcting errors in the data. |
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AbstractList | a An error correction apparatus includes: an error correction circuit for performing a data error correction based on a first error correction algorithm selected from among a plurality of error correction algorithms having different correction strengths; an error determination unit for using the first error correction algorithm to detect that the data error correction has been disabled; and a computer for selecting a second error correction algorithm from the plurality of error correction algorithms, and for controlling the error correction circuit to use the second error correction algorithm to perform the error correction for data for which it has been determined that the first error correction algorithm is not capable of correcting errors in the data. |
Author | Okamoto, Yasuhisa Naohara, Shinichi Matsuo, Kazunori Sasaki, Takashi Yoshida, Masao |
Author_xml | – sequence: 1 givenname: Takashi surname: Sasaki fullname: Sasaki, Takashi – sequence: 2 givenname: Masao surname: Yoshida fullname: Yoshida, Masao – sequence: 3 givenname: Kazunori surname: Matsuo fullname: Matsuo, Kazunori – sequence: 4 givenname: Shinichi surname: Naohara fullname: Naohara, Shinichi – sequence: 5 givenname: Yasuhisa surname: Okamoto fullname: Okamoto, Yasuhisa |
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References | Zook (4845714) 19890700 Stieger (2003/0005385) 20030100 Sugimura et al. (4653051) 19870300 Okamoto et al. (4646301) 19870200 (1 388 859) 20040200 Tidemann, Jr. et al. (6108372) 20000800 Stenfort (6457156) 20020900 Cansever et al. (6807648) 20041000 Shu Lin et al: "Automatic-Repeat-Request Error-Control Schemes", IEEE Communications Magazine, IEEE Service Center Piscataway, N.J, US, vol. 22, No. 12, Dec. 1, 1984, pp. 5-17, XP 000674086. |
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Snippet | a An error correction apparatus includes: an error correction circuit for performing a data error correction based on a first error correction algorithm... |
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