Semiconductor integrated circuit device
The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from with...
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Format | Patent |
Language | English |
Published |
04.04.2006
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Online Access | Get full text |
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Abstract | The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from within a memory array having a plurality of memory cells by a selector or selection circuit. MOSFETs constituting a precharge circuit provided for signal lines for transferring a read signal therefrom to a main amplifier are respectively brought to an on state based on a memory cell select start signal transferred to the selection circuit and brought to an off state prior to the transfer of the read signal from the memory cell to thereby complete precharging, whereby NBTI degradation at standby is avoided. |
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AbstractList | The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from within a memory array having a plurality of memory cells by a selector or selection circuit. MOSFETs constituting a precharge circuit provided for signal lines for transferring a read signal therefrom to a main amplifier are respectively brought to an on state based on a memory cell select start signal transferred to the selection circuit and brought to an off state prior to the transfer of the read signal from the memory cell to thereby complete precharging, whereby NBTI degradation at standby is avoided. |
Author | Hasegawa, Masatoshi Miyaoka, Shuichi |
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CorporateAuthor | Hitachi, Ltd |
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References | Kajigaya et al. (4893277) 19900100 Okuzawa (5517451) 19960500 Cho (6185151) 20010200 Shu et al. (5355343) 19941000 Bae et al. (6275429) 20010800 Toyoji Yamamoto, Kenichi Uwasawa, and Tohru Mogami; "Bias Temperature Instability in Scaled p+ Polysilicon Gate p-MOSFET's"; IEE Transactions on Electron Devices, vol. 46, No. 5; May 1999, pp 921-926. (10-21686) 19960600 (7-37387) 19930700 Hasegawa et al. (6865127) 20050300 Choi (5062082) 19911000 Choi (5315555) 19940500 Lee (5835449) 19981100 Kim (6026035) 20000200 Ogura (6147916) 20001100 Satani et al. (5357468) 19941000 Kawahara et al. (5539700) 19960700 Rao (5636174) 19970600 Han (6320806) 20011100 Koyanagi et al. (5659512) 19970800 Kim (6205069) 20010300 |
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Snippet | The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a... |
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