Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers

• Main Authors: Wilcox, Jeffrey R, Yosef, Noam
• Format: Patent
• Language: English
• Published: 14.02.2006

A method and apparatus for selectively disabling sense amplifiers to reduce power consumption in a memory bus interface are disclosed. The method includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence or end of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus. According to some embodiments, the disabling of the amplification may be synchronized to an edge of a delayed data strobe signal. In some embodiments, signals associated with a double data rate ("DDR") synchronous dynamic random access memory ("SDRAM") device may be communicated over the memory bus.