Stall control

Processors comprising a plurality of pipelines are disclosed, each pipeline having a plurality of pipeline stages for executing an instruction on successive clock cycles. The processors include distributed stall control circuitry which allow an instruction in one pipeline to become temporarily out o...

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Main Authors Wong, Kar-Lik Kasim, Topham, Nigel Peter
Format Patent
LanguageEnglish
Published 31.01.2006
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Abstract Processors comprising a plurality of pipelines are disclosed, each pipeline having a plurality of pipeline stages for executing an instruction on successive clock cycles. The processors include distributed stall control circuitry which allow an instruction in one pipeline to become temporarily out of step with an instruction in another pipeline. This may allow time for a global signal, such as a global stall signal, to be distributed.
AbstractList Processors comprising a plurality of pipelines are disclosed, each pipeline having a plurality of pipeline stages for executing an instruction on successive clock cycles. The processors include distributed stall control circuitry which allow an instruction in one pipeline to become temporarily out of step with an instruction in another pipeline. This may allow time for a global signal, such as a global stall signal, to be distributed.
Author Wong, Kar-Lik Kasim
Topham, Nigel Peter
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References Soltis et al. (6587940) 20030700
Tremblay et al. (6279100) 20010800
(2 348 526) 20001000
Gearty et al. (6477638) 20021100
Biswas et al. (5860000) 19990100
(00/33183) 20000600
Murty et al. (6044456) 20000300
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Snippet Processors comprising a plurality of pipelines are disclosed, each pipeline having a plurality of pipeline stages for executing an instruction on successive...
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