Fail-safe zero delay buffer with automatic internal reference
An apparatus comprising a first circuit and a second circuit. The first circuit may comprise a control circuit and an oscillator. The control circuit may be configured to generate a control signal in response to a first reference signal and a second reference signal. The oscillator may be configured...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
18.10.2005
|
Online Access | Get full text |
Cover
Loading…
Be the first to leave a comment!