Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion region
A semiconductor has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor, that are connected by a via or conductive region and interconnect. The via or conductive region contacts a bottom surface of a diffusion or source region of the transistor and...
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| Main Authors | , , , |
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| Format | Patent |
| Language | English |
| Published |
26.07.2005
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| Online Access | Get full text |
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| Abstract | A semiconductor has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor, that are connected by a via or conductive region and interconnect. The via or conductive region contacts a bottom surface of a diffusion or source region of the transistor and contacts a first of the capacitor electrodes. A laterally positioned vertical via and interconnect contacts a second of the capacitor electrodes. A metal interconnect or conductive material may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor. |
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| AbstractList | A semiconductor has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor, that are connected by a via or conductive region and interconnect. The via or conductive region contacts a bottom surface of a diffusion or source region of the transistor and contacts a first of the capacitor electrodes. A laterally positioned vertical via and interconnect contacts a second of the capacitor electrodes. A metal interconnect or conductive material may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor. |
| Author | Min, Byoung W Yu, Kathleen C Mendicino, Michael A Sanchez, Hector |
| Author_xml | – sequence: 1 givenname: Hector surname: Sanchez fullname: Sanchez, Hector – sequence: 2 givenname: Michael A surname: Mendicino fullname: Mendicino, Michael A – sequence: 3 givenname: Byoung W surname: Min fullname: Min, Byoung W – sequence: 4 givenname: Kathleen C surname: Yu fullname: Yu, Kathleen C |
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| References | Zurcher et al. (6500724) 20021200 Hayashi, Y. et al.; A New Three Dimension IC Fabrication Technology, Stack Thin Film Dual CMOS Layers, IEDN, 1991, pp. 25.6.1-25.6.4, CH3075-9/91/0000-0657, IEEE. Kadosh et al. (6358828) 20020300 Finnia (5426072) 19950600 Hsuan et al. (6252300) 20010600 Ohzu et al. (5378914) 19950100 Wu, Joyce H.; A High Aspect-Ratio Silicon Substrate-Via Technology and Applications, Master of Science in Electrical Engineering Thesis, Massachusetts Institute of Technology, Aug. 2000, pp. 1-90 (no p. 34 or 54), MIT. Armacost, M. et al.; A High Realiability Metal Insulator Metal Capacitor for 0.18 μm Copper Technology, IEEE, 2000, 4 pages, IEEE. Fung et al. (6355501) 20020300 Nishi et al. (5949140) 19990900 Schwalke et al. (5473181) 19951200 Hayashi, Y. et al.; Fabrication of Three-Dimensional IC Using "Cumulatively Bonded IC" (Cubic) Technology, 1990 Symposium on VLSI Technology, pp. 95-96; CH2874-6/90/0000-0095, IEEE. Mochizuki (5614743) 19970300 |
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| Title | Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion region |
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