One transistor SOI non-volatile random access memory cell
One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator l...
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| Format | Patent |
| Language | English |
| Published |
12.07.2005
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| Abstract | One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein. |
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| AbstractList | One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein. |
| Author | Bhattacharyya, Arup |
| Author_xml | – sequence: 1 givenname: Arup surname: Bhattacharyya fullname: Bhattacharyya, Arup |
| BookMark | eNrjYmDJy89L5WSw9M9LVSgpSswrziwuyS9SCPb3VADK6Jbl5ySWZOakKgClUvJzFRKTk1OLixVyU3PziyoVklNzcngYWNMSc4pTeaE0N4OCm2uIs4duaXFBYklqXklxfDpQM5AyMLM0NDcwtzAmQgkA9mYxIg |
| ContentType | Patent |
| CorporateAuthor | Micron Technology Inc |
| CorporateAuthor_xml | – name: Micron Technology Inc |
| DBID | EFH |
| DatabaseName | USPTO Issued Patents |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: EFH name: USPTO Issued Patents url: http://www.uspto.gov/patft/index.html sourceTypes: Open Access Repository |
| DeliveryMethod | fulltext_linktorsrc |
| ExternalDocumentID | 06917078 |
| GroupedDBID | EFH |
| ID | FETCH-uspatents_grants_069170783 |
| IEDL.DBID | EFH |
| IngestDate | Sun Mar 05 22:47:28 EST 2023 |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-uspatents_grants_069170783 |
| OpenAccessLink | https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6917078 |
| ParticipantIDs | uspatents_grants_06917078 |
| PatentNumber | 6917078 |
| PublicationCentury | 2000 |
| PublicationDate | 20050712 |
| PublicationDateYYYYMMDD | 2005-07-12 |
| PublicationDate_xml | – month: 07 year: 2005 text: 20050712 day: 12 |
| PublicationDecade | 2000 |
| PublicationYear | 2005 |
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| References_xml | – year: 20031000 ident: 6638627 – reference: Fazan, P, et al., "Capacitor-Less 1-Transistor DRAM", IEEE International SOI Conference, (2002),10-13. – year: 19860700 ident: 61-166078 – reference: Van Meer, H , "Ultra-Thin Film Fully-Depleted SOI CMOS with Raised G/S/D Device Architecture for Sub-100 nm Applications", 2001 IEEE International SOI Conference, (2001),45-6. – reference: Choi, J D., et al., "A 0.15 μm NAND Flash Technology with 0.11 μm2 Cell Size for 1 Gbit Flash Memory", IEDM Technical Digest, (2000),767-770. – reference: Lai, S K., et al., "Comparison and trends in Today's dominant E2 Technologies", IEDM Technical Digest, (1986),580-583. – year: 20040300 ident: 2004/0041206 – reference: Bauer, F, et al., "Design aspects of MOS controlled thyristor elements", International Electron Devices Meeting 1989. Technical Digest, (1989), 297-300. – year: 20031100 ident: 6653174 – year: 20030300 ident: 2003/0042534 – reference: Okhonin, S , "A SOI capacitor-less 1T-DRAM concept", 2001 IEEE International SOI Conference, Proceedings, IEEE. 2001. (2000), 153-4. – reference: Kumar, M. J., "Lateral Schottky Rectifiers for Power Integrated Circuits", International Workshop on the Physics of Semiconductor Devices,11th, 4746, Allied Publishers Ltd., New Delhi, India,(2002),414-421. – year: 20030800 ident: 2003/0160277 – year: 20040100 ident: 2004/0007734 – reference: Tiwari, Sandip, "Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage", Int'l Electron Devices Meeting: Technical Digest, Washington, DC,(Dec. 1995),521-524. – reference: Zhang, H. , "Atomic Layer Deposition of High Dielectric Constant Nanolaminates", Journal of The Electrochemical Society, 148(4), (Apr. 2001),F63-F66. – reference: Ohsawa, T , "Memory design using one-transistor gain cell on SOI", IEEE International Solid-State Circuits Conference. Digest of Technical Papers, vol. 1, (2002),152-455. – reference: Nemati, F. et al., "A Novel High Density, Low Voltage SRAM Cell With a Vertical NDR device", 1998 Symposium on VLSI Technology Digest of Technical Papers, (1998),66-7. – reference: Han, Kwangseok, "Characteristics of P-Channel Si Nano-Crystal Memory", IEDM Technical Digest, International Electron Devices Meeting, (Dec. 10-13, 2000),309-312. – year: 20030400 ident: 2003/0072126 – reference: Carter, R J., "Electrical Characterization of High-k Materials Prepared By Atomic Layer CVD", IWGI, (2001),94-99. – year: 20031100 ident: 6653175 – year: 19970500 ident: 5627779 – year: 19991100 ident: 5981335 – reference: Frohman-Bentchkowsky, D , et al., "An integrated metal-nitride-oxide-silicon (MNOS) memory", Proceedings of the IEEE, 57(6), (Jun. 1969), 1190-1192. – year: 20010600 ident: 6248626 – year: 20030800 ident: 2003/0151948 – year: 19950300 ident: 5396454 – year: 19980900 ident: 5814853 – year: 20030400 ident: 6545297 – reference: Jagar, S, "Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization", International Electron Devices Meeting 1999, Technical Digest, (1999),293-6. – year: 19881200 ident: 4791604 – year: 19991000 ident: 5963476 – year: 19960900 ident: 5557569 – year: 19980900 ident: 5801993 – year: 20010600 ident: 6243296 – year: 20030500 ident: 2003/0089942 – reference: Shinohe, T , et al., "Ultra-high di/dt 2500 V MOS assisted gate-triggered thyristors (MAGTs) for high repetition excimer laser system", International Electron Devices Meeting 1989, Technical Digest, (1989),301-4. – year: 20020400 ident: 2002/0048190 – reference: Chang, H R., et al., "MOS trench gate field-controlled thyristor", Technical Digest -International Electron Devices Meeting, (1989),293-296. – year: 20010300 ident: 6201734 – reference: Bhattacharyya, A., "Physical & Electrical Characteristics of LPCVD Silicon Rich Nitride", ECS Technical Digest, J. Eletrochem. Soc., 131(11), 691 RDP, New Orleans,(1984),469C. – reference: Sze, S. M., "Table 3: Measured Schottky Barrier Heights (Volts at 300 K)", In: Physics of Semiconductor Devices, John Wiley & Sons, Inc.,(1981),p. 291. – year: 19910800 ident: 5043946 – year: 20000800 ident: 6104045 – reference: Nemati, F, et al., "A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memories", International Electron Devices Meeting 1999, Technical Digest, (1999),283-6. – year: 20040100 ident: 2004/0014304 – year: 19960100 ident: 5488243 – year: 19760600 ident: 3964085 – year: 19760900 ident: 3978577 – year: 19970400 ident: 5621683 – year: 20010900 ident: 6294427 – year: 19751100 ident: 3918033 – year: 20030600 ident: 6574143 – year: 19890900 ident: 4870470 – year: 20030700 ident: 6600188 – year: 19841200 ident: 4488262 – year: 20021000 ident: 6462359 – year: 19890500 ident: 4829482 – year: 20020800 ident: 2002/0105023 |
| Score | 2.5801616 |
| Snippet | One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various... |
| SourceID | uspatents |
| SourceType | Open Access Repository |
| Title | One transistor SOI non-volatile random access memory cell |
| URI | https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6917078 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1NSwMxEB3aImhPior1ixy8Rptumu6ei8vqwRZU6K1kk6yXbrZ0U8R_70wqxYtCTglMwiSZNwkvLwB3wo5NUqXEbtCKS1EJjIOq5NKkpkJEc1iIbfGiinf5vBgvOlDs38LUuI34GsfS3m_bdWgiuRLD-27i-U78mTQCPakPfPpVo-3cVg8Kzx0Id13o4oqjtCgv-nCIJjBl86H9BRr5MRzMY-0JdJw_hWzmHQsEDVGZg73OnhievTnGB_TOyjFssk3NdPzCkNVEgf1idLF-Bix_fJsWfN_P8mND_JXl8Gc8yTn00Ja7ACacNapMUm1FJScTkZmhLaVzGbpL6mw0gMGfZi7_abuCo6gnSmqPo2vohc3W3SBShvI2uuEb8Ph0ow |
| linkProvider | USPTO |
| linkToPdf | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3PS8MwFH7MKf44KSrb_JWD1-iyZll7VkunshVU2K20SeplbcfaIf73ey-T4UUhpzx4ebyQ9yXhyxeAW2GG2st9YjekikuRC6yDKuNS-zpHRLPYiG0xUdGHfJ4NZy2Itm9hClxGfIGx1HeretFUjlyJ5X0z8Xwj_kwagSWpD3yV8yo1scnvFZ47EO52YFeR6BxtjMLoCA7QCW7ayqb-BRvhMezFrvcEWrY8hWBaWtYQODhtDvY2HTM8fXOsEJifuWVoMlXBUveJISuIBPvN6Gr9DFj49P4Q8e04yeeSGCxJ_yci7xza6Mt2gAlrtMo8PzUil6ORCHTfZNLaABMm02DQhe6fbnr_2G5gP34Mk9fx5OUCDp24KEk_Di6h3SxX9gphs8muXUbWzjV3mQ |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=One+transistor+SOI+non-volatile+random+access+memory+cell&rft.inventor=Bhattacharyya%2C+Arup&rft.number=6917078&rft.date=2005-07-12&rft.externalDBID=n%2Fa&rft.externalDocID=06917078 |