N-way set-associative external cache with standard DDR memory devices

A method, cache system, and cache controller are provided. A two-way and n-way cache organization scheme are presented as at least two embodiments of a set-associative external cache that utilizes standard burst memory devices such as DDR (double data rate) memory devices. The set-associative cache...

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Main Authors Wicki, Thomas M, Bennebroek, Koen R. C
Format Patent
LanguageEnglish
Published 28.06.2005
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Abstract A method, cache system, and cache controller are provided. A two-way and n-way cache organization scheme are presented as at least two embodiments of a set-associative external cache that utilizes standard burst memory devices such as DDR (double data rate) memory devices. The set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags.
AbstractList A method, cache system, and cache controller are provided. A two-way and n-way cache organization scheme are presented as at least two embodiments of a set-associative external cache that utilizes standard burst memory devices such as DDR (double data rate) memory devices. The set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags.
Author Bennebroek, Koen R. C
Wicki, Thomas M
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References Mattela et al. (6226707) 20010500
Pickett (5893146) 19990400
Shimamura et al. (6681299) 20040100
Olnowich (4493026) 19850100
(0095033) 19831100
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Snippet A method, cache system, and cache controller are provided. A two-way and n-way cache organization scheme are presented as at least two embodiments of a...
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Title N-way set-associative external cache with standard DDR memory devices
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