Method and system for testing a processor

The present invention relates to the field of test and verification of a new digital system combining software and processor hardware. In particular, the present invention relates to a method and system for verifying the correctness of the system behavior of a processor cooperating with software. A...

Full description

Saved in:
Bibliographic Details
Main Authors Boehm, Harald, von Buttlar, Joachim, Horsch, Axel, Kayser, Joerg, Koerner, Stefan, Kuenzel, Martin
Format Patent
LanguageEnglish
Published 21.12.2004
Online AccessGet full text

Cover

Loading…
Abstract The present invention relates to the field of test and verification of a new digital system combining software and processor hardware. In particular, the present invention relates to a method and system for verifying the correctness of the system behavior of a processor cooperating with software. A method for verifying the correctness of the functional behavior of a processor cooperating with software is provided. Furthermore, the method allows verification of a CPU having at least a part of its instruction set implemented with microcode. First, the microcode is independently tested by using a functional emulator performing in the same way as the processor hardware according to the processor's functional specification. Then, the microcode is tested by using a hardware emulator behaving in the same way as the processor hardware according to the design of the processor's logic gates. Finally, the microcode is tested against the actual processor hardware. This method allows the functionality of a newly designed CPU to be checked in a simulation, even before actual system integration. Advantageously, many problems in this area, relating to the interaction of the microcode and the processor hardware can be found before the actual processor hardware is manufactured. Furthermore, the ongoing verification of the newly designed CPU using the method according to the present invention allows detection of problems with the processor hardware at a relatively early stage.
AbstractList The present invention relates to the field of test and verification of a new digital system combining software and processor hardware. In particular, the present invention relates to a method and system for verifying the correctness of the system behavior of a processor cooperating with software. A method for verifying the correctness of the functional behavior of a processor cooperating with software is provided. Furthermore, the method allows verification of a CPU having at least a part of its instruction set implemented with microcode. First, the microcode is independently tested by using a functional emulator performing in the same way as the processor hardware according to the processor's functional specification. Then, the microcode is tested by using a hardware emulator behaving in the same way as the processor hardware according to the design of the processor's logic gates. Finally, the microcode is tested against the actual processor hardware. This method allows the functionality of a newly designed CPU to be checked in a simulation, even before actual system integration. Advantageously, many problems in this area, relating to the interaction of the microcode and the processor hardware can be found before the actual processor hardware is manufactured. Furthermore, the ongoing verification of the newly designed CPU using the method according to the present invention allows detection of problems with the processor hardware at a relatively early stage.
Author Kuenzel, Martin
Kayser, Joerg
Boehm, Harald
Horsch, Axel
von Buttlar, Joachim
Koerner, Stefan
Author_xml – sequence: 1
  fullname: Boehm, Harald
– sequence: 2
  fullname: von Buttlar, Joachim
– sequence: 3
  fullname: Horsch, Axel
– sequence: 4
  fullname: Kayser, Joerg
– sequence: 5
  fullname: Koerner, Stefan
– sequence: 6
  fullname: Kuenzel, Martin
BookMark eNrjYmDJy89L5WTQ9E0tychPUUjMS1EoriwuSc1VSMsvUihJLS7JzEtXSFQoKMpPTi0uzi_iYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDMwtjE2NTSmAglALY4K0c
ContentType Patent
CorporateAuthor International Business Machines Corporation
CorporateAuthor_xml – name: International Business Machines Corporation
DBID EFH
DatabaseName USPTO Issued Patents
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EFH
  name: USPTO Issued Patents
  url: http://www.uspto.gov/patft/index.html
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
ExternalDocumentID 06834359
GroupedDBID EFH
ID FETCH-uspatents_grants_068343593
IEDL.DBID EFH
IngestDate Sun Mar 05 22:37:17 EST 2023
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-uspatents_grants_068343593
OpenAccessLink https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6834359
ParticipantIDs uspatents_grants_06834359
PatentNumber 6834359
PublicationCentury 2000
PublicationDate 20041221
PublicationDateYYYYMMDD 2004-12-21
PublicationDate_xml – month: 12
  year: 2004
  text: 20041221
  day: 21
PublicationDecade 2000
PublicationYear 2004
References (WO 97/13209) 19970400
Chang et al., "Verification of a Microprocessor Using Real World Applications", Jun. 1999, IEEE, pp. 181-184.
"An Integrated CAD System for Algorithm-Specific IC Design," C. S. Shung, R. Jain, K. Rimey, E. Wang, M. Srivastava, E. Lettang, S. K. Azim, P. N. Hilfinger, J. Rabaey, R. W. Brodersen, 1989 IEEE, pp. 82-91.
Petsinger et al. (2004/0039966) 20040200
References_xml – year: 19970400
  ident: WO 97/13209
– year: 20040200
  ident: 2004/0039966
  contributor:
    fullname: Petsinger et al.
Score 2.6137881
Snippet The present invention relates to the field of test and verification of a new digital system combining software and processor hardware. In particular, the...
SourceID uspatents
SourceType Open Access Repository
Title Method and system for testing a processor
URI https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6834359
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQAdYBxolp5ma6ZmmmibqgI891k8zTTHTNEo1MzFKSzA1MksCrLfzMPEJNvCJMI5gYPOB7YXKB2Ui3AOiWYr3S4oKSfPDiSmDxDol4Xcjhz6AzAvNApw-U5-XkJ6YEpKTpm1kYA2t-S2YGZgsD0NIuVzcPbgZOoBHAJlteSTFSpeEmyMAWABYVYmBKzRNh0PQFX9asAOy6K0DOT1YANhgVSkDHXOSlKyQqFEDW7OcXiTIouLmGOHvows2NTy8CrVeJN4DabyzGwALst6dKMCikWSYbWpibgwYVLIGNfItEYNfENNkIqMrYwMIkxUiSQRKnMVJ45KQZuGCnDRoZyjCwlBSVpsoCa8aSJDmwtwEGb2zL
link.rule.ids 230,309,786,808,891,64394
linkProvider USPTO
linkToPdf http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfZ07T8MwEMdPpSAeEwgQ5emBhcGQJo6dzNAovKoMIHWLnCbuQp0occXX5-xAxQKrbZ1Otuz_nXX-GeAaNSCQSnDKVSipRZ7TQihGufQZLwvhscJVW0x5-s6eZuFsAOn6LcwStxFt0JfudtU1pnbFlXi89wtPe_izZQRqSx_41B-1LLNS3fEoQOWPN2DTaqyl6E-SdA920AgGbdp0v2Qj2YetzLUewKDSh3Dz6r5rJpi8k56gTDBkJMaCLvSCSNL0Vft1ewQkmbzdp3RtN1-0tmIl9749CI5hiJl7dQJExfNxJIS9VogxzI8kJifh3MdRgRex0h_B6E8zp__0XcF29pDkL4_T5zPY_UEP-uNzGJp2VV2gTJri0s3AF4r4b8U
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Method+and+system+for+testing+a+processor&rft.inventor=Boehm%2C+Harald&rft.inventor=von+Buttlar%2C+Joachim&rft.inventor=Horsch%2C+Axel&rft.inventor=Kayser%2C+Joerg&rft.inventor=Koerner%2C+Stefan&rft.inventor=Kuenzel%2C+Martin&rft.number=6834359&rft.date=2004-12-21&rft.externalDBID=n%2Fa&rft.externalDocID=06834359