Drain-extended MOS ESD protection structure

Not applicable. A protection structure (″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (). In a pump transistors (), the gate electrode () o...

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Main Authors Kunz, Keith E, Duvvury, Charvaka, Mosher, Dan M
Format Patent
LanguageEnglish
Published 23.09.2003
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Abstract Not applicable. A protection structure (″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (). In a pump transistors (), the gate electrode () overlaps a portion of a well () in which the drain () is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors () are connected together and to the terminal (IN), while the gates of the transistors () are connected together. The source of one transistor () is connected to a guard ring (), of the same conductivity type as the substrate () within which the channel region of the other transistors () is disposed. An ESD event received at the terminal (IN) is thus coupled to the gate of the transistors (), causing conduction to the substrate () via the guard ring (), and turning on a parasitic bipolar transistor at the other transistor (), safely conducting the ESD current. One alternative structure (′) includes a junction capacitor () coupled between the terminal (IN) and the gates of the transistors () to improve the coupling. Another alternative structure (″) includes a clamping diode () that also presents a parasitic bipolar transistor () enhancing the current conducted to the substrate ().
AbstractList Not applicable. A protection structure (″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (). In a pump transistors (), the gate electrode () overlaps a portion of a well () in which the drain () is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors () are connected together and to the terminal (IN), while the gates of the transistors () are connected together. The source of one transistor () is connected to a guard ring (), of the same conductivity type as the substrate () within which the channel region of the other transistors () is disposed. An ESD event received at the terminal (IN) is thus coupled to the gate of the transistors (), causing conduction to the substrate () via the guard ring (), and turning on a parasitic bipolar transistor at the other transistor (), safely conducting the ESD current. One alternative structure (′) includes a junction capacitor () coupled between the terminal (IN) and the gates of the transistors () to improve the coupling. Another alternative structure (″) includes a clamping diode () that also presents a parasitic bipolar transistor () enhancing the current conducted to the substrate ().
Author Duvvury, Charvaka
Kunz, Keith E
Mosher, Dan M
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References Chatterjee et al. (5907462) 19990500
Rountree et al. (4692781) 19870900
Duvvury et al.. "Substrate Pump NMOS for ESD Protection Applications", 2000 EOS/ESD Symposium, Paper 1A.2.1, pp. 7-17.
Rountre (5012317) 19910400
Duvvury (5940258) 19990800
Rountree et al., "A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes", 1998 EOS/ESD Symposium, pp. 201-205.
Duvvury et al. (4855620) 19890800
Kunz et al., "5-V Tolerant Fail-safe ESD Solutions for 0.18 um Logic CMOS Process", 2001 ESD/EOSSymposium (Sep. 11, 2001).
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Snippet Not applicable. A protection structure (″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection...
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