High voltage ESD protection device with very low snapback voltage

• Main Authors: Jiang, Jyh-Min, Liu, Kuo-Chio, Lee, Jian-Hsing, Liu, Ruey-Hsin
• Format: Patent
• Language: English
• Published: 08.07.2003

1. Field of the Invention A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted two n+ drains, one fo...