High voltage ESD protection device with very low snapback voltage

• Main Authors: Jiang, Jyh-Min, Liu, Kuo-Chio, Lee, Jian-Hsing, Liu, Ruey-Hsin
• Format: Patent
• Language: English
• Published: 08.07.2003

1. Field of the Invention A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted two n+ drains, one for each of the two transistors and a p+ diffusion separates the two n+ drains. Furthermore, the ndd area has implanted an n-well which extends from halfway under the first n+ drain to halfway under the second n+ drain. In addition, the depth of the n-well exceeds the depth of the ndd area. The added p+ diffusion together with the ndd area and the p-substrate of the silicon wafer create the parasitic pnp transistors of the SCR. The shared ndd area together with the n+ sources of the NMOS transistors creates the SCR's two parasitic npn transistors. The low triggering voltage of the SCR is achieved by the combination of the n-well, the ndd area, the p+diffusion between the two drains, and by having the two parasitic npn transistors paralleled.