Etching process
1. Field of the Invention A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
20.05.2003
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Online Access | Get full text |
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Abstract | 1. Field of the Invention
A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled by controlling the gas composition. There is provided a silicon substrate formed upon it a patterned microelectronics layer over which is formed a silicon containing dielectric layer. There is placed the silicon substrate within a reactor chamber equipped with electrodes which is evacuated. There is then filled the reactor chamber with a reactive gas mixture consisting of an oxidizing gas and two reactive gases. There may be optionally included in the reactive gas mixture nitrogen and inert gases for control purposes, but excluded from the reactive gas mixture are oxidizing gases containing carbon and oxygen. There is then formed a plasma by supplying high frequency electrical energy to the electrodes within the reactor chamber to bring about a plasma activated reactive gas etching environment, where the conditions may be selected to optimize the desired etch rate and etch rate selectivity. |
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AbstractList | 1. Field of the Invention
A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics fabrication, employing a plasma activated reactive gas mixture, with layer material etch rate, etch rate ratio and pattern aspect ratio controlled by controlling the gas composition. There is provided a silicon substrate formed upon it a patterned microelectronics layer over which is formed a silicon containing dielectric layer. There is placed the silicon substrate within a reactor chamber equipped with electrodes which is evacuated. There is then filled the reactor chamber with a reactive gas mixture consisting of an oxidizing gas and two reactive gases. There may be optionally included in the reactive gas mixture nitrogen and inert gases for control purposes, but excluded from the reactive gas mixture are oxidizing gases containing carbon and oxygen. There is then formed a plasma by supplying high frequency electrical energy to the electrodes within the reactor chamber to bring about a plasma activated reactive gas etching environment, where the conditions may be selected to optimize the desired etch rate and etch rate selectivity. |
Author | Chen, Bi-Ling Jeng, Erik S Liu, Hao-Chieh |
Author_xml | – sequence: 1 fullname: Chen, Bi-Ling – sequence: 2 fullname: Jeng, Erik S – sequence: 3 fullname: Liu, Hao-Chieh |
BookMark | eNrjYmDJy89L5WTgdy1JzsjMS1coKMpPTi0u5mFgTUvMKU7lhdLcDApuriHOHrqlxQWJJal5JcXx6UWJIMrAzNTM1NzU0pgIJQAszSGZ |
ContentType | Patent |
CorporateAuthor | Vanguard International Semiconductor Corporation |
CorporateAuthor_xml | – name: Vanguard International Semiconductor Corporation |
DBID | EFH |
DatabaseName | USPTO Issued Patents |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EFH name: USPTO Issued Patents url: http://www.uspto.gov/patft/index.html sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
ExternalDocumentID | 06565759 |
GroupedDBID | EFH |
ID | FETCH-uspatents_grants_065657593 |
IEDL.DBID | EFH |
IngestDate | Sun Mar 05 22:30:36 EST 2023 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-uspatents_grants_065657593 |
OpenAccessLink | https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6565759 |
ParticipantIDs | uspatents_grants_06565759 |
PatentNumber | 6565759 |
PublicationCentury | 2000 |
PublicationDate | 20030520 |
PublicationDateYYYYMMDD | 2003-05-20 |
PublicationDate_xml | – month: 05 year: 2003 text: 20030520 day: 20 |
PublicationDecade | 2000 |
PublicationYear | 2003 |
References | Lenz et al. (5569356) 19961000 Wang et al. (6074959) 20000600 Yi et al. (5900163) 19990500 Merry et al. (6015761) 20000100 Nulty (5562801) 19961000 Brigham et al. (5972235) 19991000 Collins (5707486) 19980100 Armacost et al. (6207353) 20010300 Bashir et al. (5856239) 19990100 Yang et al. (6165375) 20001200 Araki et al. (5770098) 19980600 |
References_xml | – year: 19991000 ident: 5972235 contributor: fullname: Brigham et al. – year: 19980600 ident: 5770098 contributor: fullname: Araki et al. – year: 19961000 ident: 5569356 contributor: fullname: Lenz et al. – year: 20000100 ident: 6015761 contributor: fullname: Merry et al. – year: 19961000 ident: 5562801 contributor: fullname: Nulty – year: 20010300 ident: 6207353 contributor: fullname: Armacost et al. – year: 20001200 ident: 6165375 contributor: fullname: Yang et al. – year: 19980100 ident: 5707486 contributor: fullname: Collins – year: 19990100 ident: 5856239 contributor: fullname: Bashir et al. – year: 19990500 ident: 5900163 contributor: fullname: Yi et al. – year: 20000600 ident: 6074959 contributor: fullname: Wang et al. |
Score | 2.5777488 |
Snippet | 1. Field of the Invention
A method for etching a pattern within a silicon containing dielectric layer upon a substrate employed within a microelectronics... |
SourceID | uspatents |
SourceType | Open Access Repository |
Title | Etching process |
URI | https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6565759 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQSbM0M0wyMEvTtTBLS9Y1MUtKAua5lFRdAxOgcoPUlBSDVNB4h6-fmUeoiVeEaQQTgwd8L0wuMBvpFgDdUqxXWlxQkg9eXAks3iERrws5_Bl0RmAe6PSB8ryc_MSUgJQ0fTPQ_J2pJTMDs4UBaGmXq5sHNwMn0Ahgky2vpBip0nATZGALAIsKMTCl5okw8LuWgNctKhRA1uaLMii4uYY4e-jCdcenF4FWpcQbQG0xFmNgAfbOUyUYFJLTksxNjZKNLZPNEk2M05KTgE2mpCSjZCPDVNNUk9Q0SQZJnMZI4ZGTZuACrxszMAUmZBkGlpKi0lRZYP1XkiQH9hwAE1lmRg |
link.rule.ids | 230,309,786,808,891,64394 |
linkProvider | USPTO |
linkToPdf | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfVzJTsMwEB2VglgOCASIsubA1eAmttucIVHYqhxA6i2qNy40jRpX_D5jB1Vc4OplbMsev7H9_ABubCqGkgpLxsIqwoSU6HPaEMqwODVaU-PvO14nonhnT1M-7UGx_gszRzciDfalvV21jVsEciVu793Ek0782WsE1l594Kv-XMx0qe2d8O93PN2ATY-xXkU_y4s92EEjGLTVrv0FG_kBbJUh9RB6pj6C_cwF5mLUdOz8Y4jy7O2-IOva1cfS81Iq-tNOcgJ9PJ-bU4iUlSMeqyRVYsYSqyQGTVLGKh4abpixAxj8aebsn7xr2C4f8urlcfJ8DruBREY5ruoL6LvlylwiGDp5Fcb5DUeFaUA |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Etching+process&rft.inventor=Chen%2C+Bi-Ling&rft.inventor=Jeng%2C+Erik+S&rft.inventor=Liu%2C+Hao-Chieh&rft.number=6565759&rft.date=2003-05-20&rft.externalDBID=n%2Fa&rft.externalDocID=06565759 |