Semiconductor memory integrated circuit employing a redundant circuit system for compensating for defectiveness
1. Field of the Invention A semiconductor memory integrated circuit is provided, which is capable of simultaneously applying voltage stress to normal signal lines and spare signal lines, thereby reducing the time required for performing a test. The semiconductor memory integrated circuit includes a...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
03.12.2002
|
Online Access | Get full text |
Cover
Loading…
Summary: | 1. Field of the Invention
A semiconductor memory integrated circuit is provided, which is capable of simultaneously applying voltage stress to normal signal lines and spare signal lines, thereby reducing the time required for performing a test. The semiconductor memory integrated circuit includes a memory cell array having a plurality of normal signal lines for selecting a memory cell, a redundant cell array including three or more of odd number of spare signal lines for compensating for defectiveness in the memory cell array, a decoder for decoding an address signal to select a normal signal line, a spare decoder, which is activated when a defective address signal is inputted, for decoding the defective address signal to select a spare signal line, and a test control circuit for controlling the decoder and the spare decoder to perform a test of applying voltage between adjacent signal lines in the normal signal lines and the spare signal lines. The test control circuit sets electric potential levels in a signal line group including the normal signal lines and the spare signal lines so that at the time of a test, electric potential levels of adjacent signal lines are opposite to each other. |
---|