Method of making differently sized vias and lines on the same lithography level
1. Field of the Invention Features of two or more distinct sizes designed to optimize performance of an integrated circuit device are formed by transferring a pattern from a resist patterned with features of a single minimum feature size for which a resist exposure tool is optimized to a layer of pr...
Saved in:
Main Authors | , , , , |
---|---|
Format | Patent |
Language | English |
Published |
03.09.2002
|
Online Access | Get full text |
Cover
Loading…
Abstract | 1. Field of the Invention
Features of two or more distinct sizes designed to optimize performance of an integrated circuit device are formed by transferring a pattern from a resist patterned with features of a single minimum feature size for which a resist exposure tool is optimized to a layer of preferably soluble material such as germanium oxide. Portions of this pattern are then enlarged using a block-out mask and the resulting pattern transferred to a further underlying layer preferably using an anisotropic reactive ion etch. The soluble material can then be removed leaving a robust mask with differing feature sizes for further processing. Preferably, Damascene conductive lines and vias are formed by providing an insulator as the further underlying material and filling the openings with metal or other conductive material. |
---|---|
AbstractList | 1. Field of the Invention
Features of two or more distinct sizes designed to optimize performance of an integrated circuit device are formed by transferring a pattern from a resist patterned with features of a single minimum feature size for which a resist exposure tool is optimized to a layer of preferably soluble material such as germanium oxide. Portions of this pattern are then enlarged using a block-out mask and the resulting pattern transferred to a further underlying layer preferably using an anisotropic reactive ion etch. The soluble material can then be removed leaving a robust mask with differing feature sizes for further processing. Preferably, Damascene conductive lines and vias are formed by providing an insulator as the further underlying material and filling the openings with metal or other conductive material. |
Author | Hakey, Mark C Furukawa, Toshiharu Horak, David V Ma, William H-L Holmes, Steven J |
Author_xml | – sequence: 1 fullname: Furukawa, Toshiharu – sequence: 2 fullname: Hakey, Mark C – sequence: 3 fullname: Holmes, Steven J – sequence: 4 fullname: Horak, David V – sequence: 5 fullname: Ma, William H-L |
BookMark | eNqNjE0KwjAUhLPQhX93mAsIRcULFEs34sa9PMhLE0xfSl8s1NMbwQM4mw-Gb2ZtFpKEV-Z25eyTRXLo6Rmkgw3O8ciS4wwNb7aYAilILGIQViRB9gylnktT1t1Ig58ReeK4NUtHUXn348agudzrdv_SgXJ51UfRv6jOp5LqcPxD-QAWsDlC |
ContentType | Patent |
CorporateAuthor | International Business Machines Corporation |
CorporateAuthor_xml | – name: International Business Machines Corporation |
DBID | EFH |
DatabaseName | USPTO Issued Patents |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EFH name: USPTO Issued Patents url: http://www.uspto.gov/patft/index.html sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
ExternalDocumentID | 06444402 |
GroupedDBID | EFH |
ID | FETCH-uspatents_grants_064444023 |
IEDL.DBID | EFH |
IngestDate | Sun Mar 05 22:30:51 EST 2023 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-uspatents_grants_064444023 |
OpenAccessLink | https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6444402 |
ParticipantIDs | uspatents_grants_06444402 |
PatentNumber | 6444402 |
PublicationCentury | 2000 |
PublicationDate | 20020903 |
PublicationDateYYYYMMDD | 2002-09-03 |
PublicationDate_xml | – month: 09 year: 2002 text: 20020903 day: 03 |
PublicationDecade | 2000 |
PublicationYear | 2002 |
References | Sebesta (4497684) 19850200 Tam (4814258) 19890300 Anderson, Jr. et al. (4519872) 19850500 Furukawa et al. (6303272) 20011000 Chu et al. (5496666) 19960300 (56-21328) 19810200 Iwadate et al. (4699870) 19871000 Saha et al. (6248664) 20010600 Lehrer et al. (4387145) 19830600 Sheppard (4533624) 19850800 Zappella et al. (5091288) 19920200 |
References_xml | – year: 19850200 ident: 4497684 contributor: fullname: Sebesta – year: 19920200 ident: 5091288 contributor: fullname: Zappella et al. – year: 19850800 ident: 4533624 contributor: fullname: Sheppard – year: 19890300 ident: 4814258 contributor: fullname: Tam – year: 19871000 ident: 4699870 contributor: fullname: Iwadate et al. – year: 19830600 ident: 4387145 contributor: fullname: Lehrer et al. – year: 19810200 ident: 56-21328 – year: 19960300 ident: 5496666 contributor: fullname: Chu et al. – year: 20011000 ident: 6303272 contributor: fullname: Furukawa et al. – year: 19850500 ident: 4519872 contributor: fullname: Anderson, Jr. et al. – year: 20010600 ident: 6248664 contributor: fullname: Saha et al. |
Score | 2.548598 |
Snippet | 1. Field of the Invention
Features of two or more distinct sizes designed to optimize performance of an integrated circuit device are formed by transferring a... |
SourceID | uspatents |
SourceType | Open Access Repository |
Title | Method of making differently sized vias and lines on the same lithography level |
URI | https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6444402 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_mENQnRcX5xT34Wu3apF2fZaUI0z0o7E3SJoFBmw7TTfSv95Lq8EWfAhdyORIud0fufgdwE8tEcC2jIAm1ogCFdC7jFLUKHoqM3NOJSF2h8OwxKV7Yw4IvBlBsa2EaUqNgRbLY27Vdda1PrqTnvb_4oAd_dhiBxqEPvJu6FXIu9R3ZdcYcquTOJHSpXdO8OIA9YkEum-nsL6ORH8Lu3FOPYKDMMTzNfLNmbDU2vgUU_jQn6eoPtMtPJXGzFBYptkfn_FlsDZJ_hlY0iii0uoeXxtpl-pwA5tPn-yLY7v5K024Iv6WMT2FI0b06A9RjOU6iqio5K1lUxUKnSapUKlmVSR7rEYz-ZHP-z9wF7PvGJe7vI76EYfe2VldkP7vy2h_OF0qzfH8 |
link.rule.ids | 230,309,786,808,891,64396 |
linkProvider | USPTO |
linkToPdf | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LT8MwDLamgXicQIAYTx-4Frq2aekZVpXHRg8g7TalTSJN6mMiHQh-PU4KExc4RYqVxMrLnxXnM8CFL0LOlPCc0FWSHBQ6czEjr5Uzl8cET695ZD4Kjydh-hLcT9m0B-nqL0xFx8hZkC76cqkXbWODK-l67xbe6cifDUdgbdgH3uuy4SIT6orsehAYVsk1Y2PNXh8l6TZsUicE2upW_zIbyQ6sZ7Z2F3qy3oOnsU3XjI3CyiaBwp_0JG35gXr-KQW-zblG8u7RwD-NTY2E0FDzSlINte4IprE0sT77gMno-SZ1VqPPSGwK91tP_wD65N_LQ0A1FMPQK4qcBXngFT5XURhJGYmgiAXz1QAGf3Zz9I_sHDay22T2eDd5OIYtm8XEPIT4J9BvX5fylIxpm5_ZefoCjht_ew |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Method+of+making+differently+sized+vias+and+lines+on+the+same+lithography+level&rft.inventor=Furukawa%2C+Toshiharu&rft.inventor=Hakey%2C+Mark+C&rft.inventor=Holmes%2C+Steven+J&rft.inventor=Horak%2C+David+V&rft.inventor=Ma%2C+William+H-L&rft.number=6444402&rft.date=2002-09-03&rft.externalDBID=n%2Fa&rft.externalDocID=06444402 |