Method for hierarchical parasitic extraction of a CMOS design

• Main Authors: Cano, Francisco A, Savithri, Nagaraj N, Gunturi, Vijaya
• Format: Patent
• Language: English
• Published: 26.03.2002

This application is related to co-assigned application Ser. No. 09/608,309 filed contemporaneously herewith and incorporated herein by reference. In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on...