Copper recess process with application to selective capping and electroless plating

An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the condu...

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Main Authors Dalton, Timothy, Chen, Shyng-Tsong, Davis, Kenneth, Hu, Chao-Kun, Jamin, Fen, Kaldor, Steffen, Krishnan, Mahadevaiyer, Kumar, Kaushik, Lofaro, Michael, Malhotra, Sandra, Narayan, Chandrasekhar, Rath, David, Rubino, Judith, Saenger, Katherine, Simon, Andrew, Smith, Sean, Tseng, Wei-tsu
Format Patent
LanguageEnglish
Published 17.06.2004
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Summary:An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.