METHOD AND APPARATUS FOR A HIGH FREQUENCY, LOW POWER CLOCK DISTRIBUTION WITHIN A VLSI CHIP

A method and apparatus are provided for a high frequency, low power clock distribution within a very large scale integrated (VLSI) circuit chip. The apparatus for a high frequency, low power clock distribution within a very large scale integrated (VLSI) circuit chip includes a first clock circuit ge...

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Bibliographic Details
Main Authors STASIAK, DANIEL LAWRENCE, STROM, JAMES DAVID, TRAN, JEFF V
Format Patent
LanguageEnglish
Published 23.05.2002
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Summary:A method and apparatus are provided for a high frequency, low power clock distribution within a very large scale integrated (VLSI) circuit chip. The apparatus for a high frequency, low power clock distribution within a very large scale integrated (VLSI) circuit chip includes a first clock circuit generating a first clock signal. A first level inverter is coupled to the first clock circuit receiving the first clock signal. A clock multiplier is coupled to the first level inverter, generating a multiplied clock signal. A plurality of inverters are coupled to the clock multiplier for driving logic circuits within the VLSI circuit chip at the multiplied clock signal.